8a46b71411
phy/model: cleanup indent, avoid too long lines.
2020-02-13 17:25:37 +01:00
fc06a864e5
phy/model: use " instead of ' (as we are usually doing)
2020-02-13 17:02:55 +01:00
8594e12b3a
phy/model: update TODO
2020-02-13 16:57:47 +01:00
5d9b28aa10
Merge pull request #138 from antmicro/dfi-timings-checker
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phy/model: add basic timing violation checker
2020-02-13 16:52:33 +01:00
94aaa06bce
phy/model: add option to disable timings checker and enable verbose output
2020-02-13 14:22:35 +01:00
d71764d47e
Merge pull request #141 from antmicro/jboc/benchmark
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Benchmark: reduce disk usage when running benchmarks in parallel
2020-02-13 14:00:17 +01:00
804e74985c
phy/model: add basic timing violation checker
2020-02-13 13:54:27 +01:00
dd12a78587
test: reduce disk usage when running benchmarks in parallel
2020-02-13 10:30:48 +01:00
4febb2a6aa
Merge pull request #140 from antmicro/jboc/benchmark
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Benchmark: use variable number of BIST generators/checkers
2020-02-12 16:56:31 +01:00
5cd33f490f
test: update benchmark configuration generator
2020-02-12 15:42:50 +01:00
4f613b5b00
test: add number of generators/checkers to benchmark runner, update metrics
2020-02-12 14:40:33 +01:00
edf4ddb2f2
test: add option to use multiple BIST generators/checkers
2020-02-12 14:40:33 +01:00
354139959a
fix: code formatting
2020-02-12 14:40:33 +01:00
38fe8a81dd
Merge pull request #139 from enjoy-digital/travis-ci
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travis-ci: avoid use of conda (setup is simple enough to avoid it)
2020-02-12 10:47:18 +01:00
8316ed3a47
travis-ci: avoid use of conda (setup is simple enough to avoid it)
2020-02-12 10:28:37 +01:00
cd4e007a27
Merge pull request #128 from antmicro/linux-ci
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Add simulations to Travis CI
2020-02-12 08:23:40 +01:00
0904d8bc4d
Merge pull request #137 from antmicro/jboc/benchmark
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Benchmark: add simultaneous Write/Read and random address generation
2020-02-12 08:13:49 +01:00
45633e55b5
test: update BIST generator and checker tests
2020-02-11 14:24:02 +01:00
409b9922ea
test: add random address generation in benchmarks
2020-02-11 13:11:06 +01:00
abf6d1c3d6
test: add random address generation to BIST
2020-02-11 13:10:10 +01:00
6744cf649c
test: add handling of alternating write/read to benchmark runner
2020-02-11 13:10:04 +01:00
e16118abfd
test: fix: use of undeclared variable
2020-02-11 12:13:37 +01:00
ff435fd26e
test: add option to run benchmarks with alternating write/read
2020-02-11 12:06:45 +01:00
6093f2012e
test: add run/ready signals to BIST modules
2020-02-11 11:45:01 +01:00
831eadcc6d
travis: add simulation tests
2020-02-11 02:22:25 +01:00
ca17cfd83d
frontend/wishbone: round port_data_width to lowest power of 2 (required for ECC cases)
2020-02-10 09:56:36 +01:00
ad173d69fb
Merge pull request #136 from antmicro/jboc/benchmark
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Benchmark: use Memory instead of Case for custom access pattern
2020-02-08 09:27:27 +01:00
cf5939f09e
test: use Memory instead of Case for custom access pattern
2020-02-07 14:58:33 +01:00
ab8661405a
Merge pull request #135 from antmicro/jboc/benchmark
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Improve speed of benchmark runner
2020-02-07 12:41:29 +01:00
9148400ef5
test: fix typo, add note about limitations
2020-02-07 12:20:43 +01:00
2825c080a9
test: fix problem with plot labels overlapping for large number of benchmarks
2020-02-07 09:52:31 +01:00
08fd2960d0
Merge pull request #131 from antmicro/jboc/benchmark
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Allow testing custom access patterns
2020-02-06 18:12:35 +01:00
77541c3670
test: avoid instantiating LiteDRAMBenchmarkSoC to speed up summary generation
2020-02-06 15:08:01 +01:00
027034db49
test: add option to run benchmarks as parallel jobs
2020-02-06 15:07:55 +01:00
62a5473ecd
test: update script for generating benchmark configurations
2020-02-06 13:35:34 +01:00
c2051df1c3
Merge pull request #132 from antmicro/modules-fix-syntax-error
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modules: MT18KSF1G72HZ: use float as tWR value
2020-02-06 09:43:43 +01:00
8ba3cced60
test: add new benchmark configuratiosns to example configuration file
2020-02-05 18:58:49 +01:00
1702e2ad7c
test: update summary to work for all configurations (use pandas)
2020-02-05 18:39:06 +01:00
6595567fa8
modules: MT18KSF1G72HZ: use float as tWR value
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Fixes error:
$ litex_sim --with-sdram --sdram-module MT18KSF1G72HZ
Traceback (most recent call last):
File "bin/litex_sim", line 11, in <module>
load_entry_point('litex', 'console_scripts', 'litex_sim')()
File "litex/litex/tools/litex_sim.py", line 301, in main
**soc_kwargs)
File "litex/litex/tools/litex_sim.py", line 187, in __init__
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
File "litedram/litedram/modules.py", line 65, in __init__
File "litedram/litedram/modules.py", line 110, in ns_to_cycles
TypeError: can only concatenate tuple (not "float") to tuple
2020-02-05 15:41:28 +01:00
f9f86d507f
test: update benchmark configuration to account for access pattern
2020-02-05 12:54:33 +01:00
7e0515c477
test: fix problem with helper scripts being executed by `setup.py test`
2020-02-04 16:37:26 +01:00
fcd3d4ff6c
test: helper scripts for generating benchmark configurations/access patterns
2020-02-04 16:26:57 +01:00
fcbcd4d3fe
test: add option to benchmark predefined access patterns
2020-02-04 16:26:57 +01:00
4a3ad56146
Merge pull request #129 from antmicro/8-16-bit-init
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phy/model: add support for 8/16-bit wide SDR memory init
2020-02-04 11:29:28 +01:00
6fd8f2172f
phy/model: add support for 8/16-bit wide SDR memory init
2020-02-04 10:51:56 +01:00
586980a4e5
frontend/dma: test and fix add_csr on DMAs
2020-02-03 19:47:49 +01:00
c536330e36
Merge pull request #127 from antmicro/jboc/benchmark
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Add Write/Read latency measurement
2020-02-03 19:04:48 +01:00
bae046f143
test: add read/write latency benchmarks
2020-02-03 16:59:12 +01:00
9aa421e52a
Merge pull request #125 from antmicro/fix-init
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phy/model: fix case when not converting init data width
2020-02-03 15:09:49 +01:00
4c86235048
phy/model: fix case when not converting init data width
2020-02-03 13:35:49 +01:00
Florent Kermarrec
Piotr Binkowski
Jędrzej Boczar
Mariusz Glebocki