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Author SHA1 Message Date
Florent Kermarrec
6fc6174c38 bench/genesys2: expose uart parameter. 2020-09-17 08:22:17 +02:00
Florent Kermarrec
8525a27762 test/reference: update. 2020-09-15 20:00:55 +02:00
Florent Kermarrec
8d39ac6dd1 phy/s7ddrphy: remove interface_type parameter and ISERDESE2's MEMORY_MODE support. 
Supporting MEMORY_MODE add complexity to the codebase and this mode is not used by anyone.
It has been experimented on NeTV2 to solves instability at low temperature but hasn't improved
the behaviour.
 2020-09-15 19:55:58 +02:00
Florent Kermarrec
c3b4b0d338 phy/s7ddrphy: reduce BitSlip's cycles to 1 (seems to be enough for all cases). 2020-09-15 19:50:45 +02:00
Florent Kermarrec
26e45d1ce4 phys: add support for dynamic rd/rdcmd/wr/wrcmd phases. 2020-09-14 18:57:20 +02:00
Florent Kermarrec
6a5f2fdb09 bench/genesys2: add uart_name parameter. 
Useful when Etherbone is just used to reload BIOS.
 2020-09-14 18:43:33 +02:00
Florent Kermarrec
f5184b41b5 core/multiplexer/steerel_sel: add support for dynamic rd/rdcmd/wr/wrcmd phases. 
This is useful for development and also simplifies code (without using more resources when constants are used).
 2020-09-14 18:40:58 +02:00
Florent Kermarrec
020cff1970 bench/genesys2: add back Etherbone (faster for BIOS dev) and add --load-bios/set-sys_clk arguments. 2020-09-14 10:55:16 +02:00
Florent Kermarrec
6a75aa0ad7 bench/common: add s7_load_bios/s7_set_sys_clk functions. 2020-09-14 10:54:35 +02:00
Florent Kermarrec
7eeea34c4e bench: use 115200bauds UART on all targets (fast enough and simplify switch betwen targets). 2020-09-14 10:05:55 +02:00
Florent Kermarrec
e56f74e08b test/reference: update. 2020-09-07 19:37:03 +02:00
Florent Kermarrec
cf45ca48bc s7ddrphy/usddrphy: add cmd_delay parameter and pass cmd_latency/cmd_delay to PhySettings/Software. 2020-09-07 18:50:01 +02:00
Florent Kermarrec
3bab6f2024 common/PHYPadsReducer: make Cat optional (disabled by default). 2020-09-04 11:10:48 +02:00
Florent Kermarrec
543a94dd33 bench/common: enable load_rom on kcu105 (with delay workaround). 2020-09-03 17:46:50 +02:00
Florent Kermarrec
41c8ac637d common/PHYPadsReducer: add Cat around Array (helps for standalone core integration). 2020-09-02 09:40:14 +02:00
Florent Kermarrec
d5fa60240b litedram/gen: update LiteDRAMECP5DDRPHYCRG (AsyncResetSynchronizer integrated in PLL). 2020-09-01 13:58:16 +02:00
Florent Kermarrec
7d9c1de0a4 modules: remove unnecessary memtypes. 2020-09-01 13:43:09 +02:00
Florent Kermarrec
7d0dac78c5 bench/kcu105: add a second pll to reduce frequency steps. 2020-08-28 19:03:44 +02:00
Florent Kermarrec
0412dbd01d phy/usddrphy: add global rst CSR and set default cmd_latency to 1. 2020-08-28 18:49:33 +02:00
Florent Kermarrec
1fb78fa558 bench: cleanup, do more testing on 7-series. 2020-08-28 17:57:59 +02:00
Florent Kermarrec
f43cfad4e3 phy/s7ddrphy: add global rst CSR and set default cmd_latency to 1 on Kintex7/Ultrascale. 2020-08-28 17:56:48 +02:00
Florent Kermarrec
248c5de517 bench: switch to UARTBone to simplify (and to allow testing boards without ethernet capability) and improve test. 2020-08-28 03:47:49 +02:00
Florent Kermarrec
6f2462b731 bench: add kc705. 2020-08-27 19:05:17 +02:00
Florent Kermarrec
d3502e6a9b bench: add common.py with common bench test code. 2020-08-27 19:05:05 +02:00
Florent Kermarrec
2e3e19e9d4 bench: simplify/improve, working on arty/genesys2. 2020-08-27 18:41:54 +02:00
Florent Kermarrec
5c69da5d6d bench: add initial kcu105 bench target. 2020-08-24 21:56:11 +02:00
Florent Kermarrec
9995c0fefb bench: switch integrated_rom to "rw" mode and reload it over Etherbone at startup. 
This simplifies software development.
 2020-08-24 18:40:54 +02:00
Florent Kermarrec
ac825e5112 add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
Florent Kermarrec
198bcbab67 test/reference: update. 2020-08-07 23:14:09 +02:00
Florent Kermarrec
e3b86fef70 getting started: update. 2020-08-07 23:06:24 +02:00
Florent Kermarrec
a0a886e856 litedram/init: export xdr ratio and databits. 2020-08-07 19:47:27 +02:00
Florent Kermarrec
94241d0583 bench: use new platform.request_all on LedChaser. 2020-08-06 20:03:03 +02:00
Florent Kermarrec
74205979bd bench: add genesys2 bench. 2020-08-06 19:19:45 +02:00
Florent Kermarrec
37fb44f33e add bench directory with a first bench on arty board. 
The aim is to create an automated hardware bench, control is done over Etherbone
(but could also be done over UARTBone, PCIe, USB, etc...) and various frequencies
are tested and BIOS logged.

It would also be useful to be able to recompile/reload BIOS in this bench to easily
test software changes and verify it works with various frequencies.

Can be tested with:
./arty.py --build --load
lxserver --udp
./arty.py --test
Dump Main PLL...
ClkReg1:
  low_time:  8
  high_time: 8
  reserved:  1
  phase_mux: 0
Reconfig Main PLL to 133.33333333333331MHz...
Measuring sys_clk...
sys_clk: 133.72MHz
Reset SoC and get BIOS log...

        __
        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Aug  6 2020 18:49:15
 BIOS CRC passed (44c8f057)

 Migen git sha1: 7bc4eb1
 LiteX git sha1: 188e6f57

--=============== SoC ==================--
CPU:       VexRiscv @ 100MHz
BUS:       WISHBONE 32-bit @ 4GiB
CSR:       32-bit data
ROM:       32KiB
SRAM:      8KiB
L2:        8KiB
MAIN-RAM:  262144KiB

--========== Initialization ============--
Initializing DRAM @0x40000000...
SDRAM now under software control
SDRAM now under software control
Read leveling:
m0, b00: |00000000000000000000000000000000| delays: -
m0, b01: |00000000000000000000000000000000| delays: -
m0, b02: |00000000000000000000000000000000| delays: -
m0, b03: |00000000000000000000000000000000| delays: -
m0, b04: |00000000000000000000000000000000| delays: -
m0, b05: |00000000000000000000000000000000| delays: -
m0, b06: |00000000000000000000000000000000| delays: -
m0, b07: |00000000000000000000000000000000| delays: -
m0, b08: |00000000000000000000000000000000| delays: -
m0, b09: |11111111111000000000000000000000| delays: 05+-05
m0, b10: |00000000000111111111110000000000| delays: 16+-05
m0, b11: |00000000000000000000000111111111| delays: 27+-04
m0, b12: |00000000000000000000000000000000| delays: -
m0, b13: |00000000000000000000000000000000| delays: -
m0, b14: |00000000000000000000000000000000| delays: -
m0, b15: |00000000000000000000000000000000| delays: -
best: m0, b09 delays: 05+-05
m1, b00: |00000000000000000000000000000000| delays: -
m1, b01: |00000000000000000000000000000000| delays: -
m1, b02: |00000000000000000000000000000000| delays: -
m1, b03: |00000000000000000000000000000000| delays: -
m1, b04: |00000000000000000000000000000000| delays: -
m1, b05: |00000000000000000000000000000000| delays: -
m1, b06: |00000000000000000000000000000000| delays: -
m1, b07: |00000000000000000000000000000000| delays: -
m1, b08: |00000000000000000000000000000000| delays: -
m1, b09: |11111111111000000000000000000000| delays: 05+-05
m1, b10: |00000000000011111111111000000000| delays: 17+-05
m1, b11: |00000000000000000000000011111111| delays: 28+-04
m1, b12: |00000000000000000000000000000000| delays: -
m1, b13: |00000000000000000000000000000000| delays: -
m1, b14: |00000000000000000000000000000000| delays: -
m1, b15: |00000000000000000000000000000000| delays: -
best: m1, b09 delays: 05+-05
SDRAM now under hardware control
Memtest at 0x40000000...
[########################################]
[########################################]
Memtest OK
Memspeed at 0x40000000...
Writes: 212 Mbps
Reads:  188 Mbps

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--


litex> Reconfig Main PLL to 114.28571428571428MHz...
 2020-08-06 19:05:20 +02:00
Florent Kermarrec
4e62d28af6 examples/.yml: set cmd_latency to 1 on Kintex7/Ultrascale (values valided in LiteX-Boards). 2020-08-06 11:52:34 +02:00
Florent Kermarrec
07bf34d0e7 frontend/wishbone: revert non-FSM version, the FSM one does not seem to cover all cases. 2020-08-05 15:48:23 +02:00
Florent Kermarrec
9c5ce52b88 common: add connect method to LiteDRAMNativePort and use it in adapter for identify converter. 2020-08-05 12:17:25 +02:00
Florent Kermarrec
06f7192fb6 frontend/adapter/LiteDRAMNativePortConverter: simplify using ratio. 2020-08-05 11:41:54 +02:00
Florent Kermarrec
a3dfc1db25 frontend/adapter: minor cleanups. 2020-08-05 11:34:49 +02:00
Florent Kermarrec
deac4c8134 frontend/adapter: simplify LiteDRAMNativePortDownConverter. 2020-08-05 11:28:44 +02:00
Florent Kermarrec
ce4e7f9ad0 frontend/adapter: simplify LiteDRAMNativePortCDC using stream.ClockDomainCrossing. 2020-08-05 11:24:48 +02:00
Florent Kermarrec
16fd46bf35 frontend: rename adaptation to adapter. 2020-08-05 11:10:42 +02:00
Florent Kermarrec
4970c8aa8c frontend/wishbone: simplify/review and get FSM back (ease comprehension). 2020-08-05 11:05:00 +02:00
Florent Kermarrec
47a0d5fb9e litedram_gen/LiteDRAMUSDDRPHYCRG: remove AsyncResetSynchronizer on sys/sys4x (reset handled by USIDELAYCTRL). 2020-07-29 08:12:49 +02:00
enjoy-digital
02e67ec7c5
Merge pull request #192 from antmicro/jboc/port-adaptation 
Implement LiteDRAMNativePortUpConverter with mode="both"
 2020-07-28 19:02:33 +02:00
enjoy-digital
71b991ec08
Merge pull request #210 from oskirby/ddr3-tdqs-mode 
Add support for TDQS mode.
 2020-07-27 10:52:48 +02:00
Owen Kirby
805a37447c Add support for TDQS mode. 
This adds an optional argument to add_electrical_settings() that can
enable the TDQS mode for x8 DDR3 modules. Normally this would be used
when mixing x4 and x8 modules (eg: heterogenous DIMMS), but it can
also workaround boards with missing or broken DM signals.
 2020-07-26 15:51:07 -07:00
Florent Kermarrec
c01e86865f phy/gensdrphy/HalfRateGENSDRPHY: review/simplify and reduce read_latency by 1. 2020-07-24 11:07:15 +02:00
Florent Kermarrec
f51052f8b7 core/controller: fix burst_length regression introduced by #206. 2020-07-18 23:06:11 +02:00
enjoy-digital
c4ac887ec2
Merge pull request #206 from antmicro/jboc/gensdrphy 
Add HalfRate GENSDRPHY
 2020-07-15 08:19:37 +02:00