72b1b109b7
Fix all remaining indentation issues in python code
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I ran a script that shouldn't have missed any tab in the python source files.
2018-01-13 13:22:08 +11:00
a09b7a05b8
phy/kusddrphy: typo
2017-12-08 16:10:10 +01:00
010a6a2b91
phy/kusddrphy: use initial delay value on dqs instead of shifted sys4x clock
2017-12-08 15:52:52 +01:00
26d60fa781
doc: add simple architecture diagram
2017-11-13 18:49:35 +01:00
eb6010d784
phy/kusddrphy: use locally inverted clk_b on iserdese3
2017-11-10 00:46:20 +01:00
38f1c268e9
phy/kusddrphy: reset bitslip on wdly_dq_rst instead of rdly_dq_rst
2017-11-08 21:52:56 +01:00
f31f8a03ff
modules: add MT46H32M32
2017-07-25 10:34:03 +02:00
47755e5637
phy/kusddrphy: fix typo on oserdese3/odatain (no functional impact)
2017-07-12 08:43:14 +02:00
f251800fb6
phy/kusddrphy: use similar bitslip interface than kintex7
2017-07-10 15:50:47 +02:00
40a8504dd6
phy/kusddrphy: use specific sys4x_dqs clock since we can't ensure initial delay between dq/dqs using odelaye3 on ultrascale...
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tap delay can vary from 2.5 to 15ps across PVT
2017-07-10 14:39:54 +02:00
5977a6fca0
phy/kusddrphy: remove comment on idelaye3 initial delay since fully covered by software
2017-07-10 13:59:24 +02:00
86b0cc0a56
frontend/bist: restrict lfsr to 32 bit allow bist with large ddram
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msbs data are then filled with zeros, but we should fix lfsr generation to avoid this
2017-07-10 12:02:13 +02:00
33ca8d604e
frontend/bist: use bytes for base and length parameters
2017-07-10 10:02:41 +02:00
7b31005bc4
phy/kusddrphy: fix input bit ordering, working :)
2017-07-08 18:46:53 +02:00
99fe71d622
phy/kusddrphy: revert delays control and add comments for initial delays values
2017-07-08 10:54:02 +02:00
aad2f92b33
phy/kusddrphy: IOBUF incorrect behaviour fixed by upgrading vivado to 2017.2...
2017-07-08 10:13:58 +02:00
a72ba87f3e
phy/kusddrphy: use fixed delays for initial board test, identify strange behaviour of IOBUF...
2017-07-08 09:41:08 +02:00
7ea734381e
phy/kusddrphy: phy has been simulated, remove from TODO
2017-07-07 09:03:54 +02:00
b21a9d8e18
phy/kusddrphy: add phy reset (just to be sure primitives are correctly reseted, will be removed if not needed)
2017-07-07 09:02:58 +02:00
fa3535f7c0
phy/kusddrphy: verify latencies with simulation
2017-07-06 19:21:38 +02:00
abf028e0be
global: reset_less optimizations
2017-07-01 11:18:05 +02:00
67df00bcac
frontend/bist: use new reset_less attribute where possible
2017-06-29 11:20:08 +02:00
c8713bfb48
litedram/frontend/bist: cleanup and add ticks counters to measure performance with hardware
2017-06-29 10:41:34 +02:00
6091c6de60
frontend: remove fifo, too complex to get working and too many corner cases (data stuck in pipeline, ...)
2017-06-28 12:30:59 +02:00
369e9308b9
frontend/fifo: simplify and only keep raw layout
2017-06-27 17:24:32 +02:00
883e97101a
common: add id to ports
2017-06-27 15:06:12 +02:00
9ce2f67bb1
frontend: add dram fifo (untested)
2017-06-23 22:00:49 +02:00
bab0150c87
README: consistency between projects
2017-06-22 16:57:14 +02:00
25d5674f33
test: remove test_bitslip (now in litex)
2017-04-24 18:49:20 +02:00
3fe29ddacc
phy: BitSlip now integrated in LiteX
2017-04-19 09:58:27 +02:00
767b0144eb
modules: add MT41J256M16
2017-03-14 20:59:02 +01:00
ddb05b92b6
phy/kusddrphy: test implementation and fixes
2017-03-14 09:20:06 +01:00
c04c288e66
phy/kusddrphy: fix OSERDESE3/ISERDESE3 data ports
2017-03-09 10:54:53 +01:00
98d9f1ffc0
test/test_bitslip: simplify BitSlipModel
2017-02-10 13:18:11 +01:00
cd83448f8e
README: update copyright
2017-02-10 13:08:09 +01:00
63434324e6
phy/kusddrphy: add TODO
2017-02-10 13:05:49 +01:00
ac43e0118e
phy/x7ddrphy: ease understanding of read latency loop range
2017-02-10 12:57:08 +01:00
478b8c1df3
phy/kusddrphy: integrate BitSlip module (in fabric) and instanciate ISERDESE3
2017-02-10 12:51:30 +01:00
c94b1e7d0a
phy: cleanup instances indentation
2017-02-10 10:06:31 +01:00
062177502b
phy: add bitslip module (we need to implement it in logic for Kintex Ultrascale since not provided by ISERDESE3)
2017-02-10 08:59:13 +01:00
1430cb3d49
phy: add initial Kintex Ultrascale PHY (incomplete)
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Input deserializer still missing, need to implement bitslip in logic and use new fifo interface.
Others primitives should be fine.
2017-02-09 13:25:45 +01:00
99550968e7
test: move BISTDriver to common and use it in test_bist_async
2017-01-17 15:18:10 +01:00
1bcab6303d
setup.py: add test_suite
2017-01-17 15:17:21 +01:00
d213a628f8
test/test_bist: use generator to corrupt memory (allow testing base address on checker/generator)
2017-01-17 14:35:34 +01:00
40168db0b4
test/test_bist: create BISTDriver to simplify test code
2017-01-17 14:31:24 +01:00
4f51524921
frontend/bist: rename err_count to errors
2017-01-17 14:30:23 +01:00
c56f90e865
test/test_bist: simplify and test modules directly not through CSR
2017-01-17 14:14:50 +01:00
e7fe539c73
frontend/bist: remove LiteDRAMBISTCheckerScope.
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Checker should not be used to investigate errors but only to verify that is already validated still works. (ie we don't want to be able to understand what is going on, just to know if it's working or not). To understand what is going on we will look at signals with LiteScope and eventually trigger on err_count from checker.
2017-01-17 13:48:03 +01:00
ad304c8997
test: convert to python unittests and some cleanup
2017-01-17 13:18:11 +01:00
53d11cf7e3
Merge pull request #5 from mithro/scope
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Creating a utility module for easily scoping the LiteDRAMBISTChecker module.
2016-12-24 15:16:36 +01:00
Felix Held
Florent Kermarrec