831eadcc6d
travis: add simulation tests
2020-02-11 02:22:25 +01:00
ca17cfd83d
frontend/wishbone: round port_data_width to lowest power of 2 (required for ECC cases)
2020-02-10 09:56:36 +01:00
ad173d69fb
Merge pull request #136 from antmicro/jboc/benchmark
...
Benchmark: use Memory instead of Case for custom access pattern
2020-02-08 09:27:27 +01:00
cf5939f09e
test: use Memory instead of Case for custom access pattern
2020-02-07 14:58:33 +01:00
ab8661405a
Merge pull request #135 from antmicro/jboc/benchmark
...
Improve speed of benchmark runner
2020-02-07 12:41:29 +01:00
9148400ef5
test: fix typo, add note about limitations
2020-02-07 12:20:43 +01:00
2825c080a9
test: fix problem with plot labels overlapping for large number of benchmarks
2020-02-07 09:52:31 +01:00
08fd2960d0
Merge pull request #131 from antmicro/jboc/benchmark
...
Allow testing custom access patterns
2020-02-06 18:12:35 +01:00
77541c3670
test: avoid instantiating LiteDRAMBenchmarkSoC to speed up summary generation
2020-02-06 15:08:01 +01:00
027034db49
test: add option to run benchmarks as parallel jobs
2020-02-06 15:07:55 +01:00
62a5473ecd
test: update script for generating benchmark configurations
2020-02-06 13:35:34 +01:00
c2051df1c3
Merge pull request #132 from antmicro/modules-fix-syntax-error
...
modules: MT18KSF1G72HZ: use float as tWR value
2020-02-06 09:43:43 +01:00
8ba3cced60
test: add new benchmark configuratiosns to example configuration file
2020-02-05 18:58:49 +01:00
1702e2ad7c
test: update summary to work for all configurations (use pandas)
2020-02-05 18:39:06 +01:00
6595567fa8
modules: MT18KSF1G72HZ: use float as tWR value
...
Fixes error:
$ litex_sim --with-sdram --sdram-module MT18KSF1G72HZ
Traceback (most recent call last):
File "bin/litex_sim", line 11, in <module>
load_entry_point('litex', 'console_scripts', 'litex_sim')()
File "litex/litex/tools/litex_sim.py", line 301, in main
**soc_kwargs)
File "litex/litex/tools/litex_sim.py", line 187, in __init__
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
File "litedram/litedram/modules.py", line 65, in __init__
File "litedram/litedram/modules.py", line 110, in ns_to_cycles
TypeError: can only concatenate tuple (not "float") to tuple
2020-02-05 15:41:28 +01:00
f9f86d507f
test: update benchmark configuration to account for access pattern
2020-02-05 12:54:33 +01:00
7e0515c477
test: fix problem with helper scripts being executed by `setup.py test`
2020-02-04 16:37:26 +01:00
fcd3d4ff6c
test: helper scripts for generating benchmark configurations/access patterns
2020-02-04 16:26:57 +01:00
fcbcd4d3fe
test: add option to benchmark predefined access patterns
2020-02-04 16:26:57 +01:00
4a3ad56146
Merge pull request #129 from antmicro/8-16-bit-init
...
phy/model: add support for 8/16-bit wide SDR memory init
2020-02-04 11:29:28 +01:00
6fd8f2172f
phy/model: add support for 8/16-bit wide SDR memory init
2020-02-04 10:51:56 +01:00
586980a4e5
frontend/dma: test and fix add_csr on DMAs
2020-02-03 19:47:49 +01:00
c536330e36
Merge pull request #127 from antmicro/jboc/benchmark
...
Add Write/Read latency measurement
2020-02-03 19:04:48 +01:00
bae046f143
test: add read/write latency benchmarks
2020-02-03 16:59:12 +01:00
9aa421e52a
Merge pull request #125 from antmicro/fix-init
...
phy/model: fix case when not converting init data width
2020-02-03 15:09:49 +01:00
4c86235048
phy/model: fix case when not converting init data width
2020-02-03 13:35:49 +01:00
a903c87872
Merge pull request #124 from antmicro/l2-reverse
...
phy/model: cleanup the memory init code
2020-02-03 12:55:02 +01:00
a584923f1c
test: use JSON instead of pickle for storing benchmarks cache
2020-02-03 12:17:41 +01:00
99227ad0d0
phy/model: cleanup the memory init code
...
After adding support for l2_reverse flag in Cache/SoCSDRAM we can remove
code responsible for word order reversing and do a general cleanup
2020-02-03 12:02:49 +01:00
736723cc98
test/run_benchmarks: change YAML config file argument
2020-02-03 10:38:10 +01:00
7e95ecc9a9
test/run_benchmark: avoid Python 3.7+ dependency
2020-02-03 10:37:10 +01:00
d8f3feb971
Merge pull request #123 from antmicro/jboc/benchmark
...
Add plotting of benchmark results
2020-02-03 10:35:09 +01:00
811c73254b
test: benchmark script exits with error on any checker error
2020-01-31 15:16:37 +01:00
1a517a308d
test: cache benchmark results to be able to produce multiple summaries
2020-01-31 14:39:41 +01:00
a40817f3a8
test: add plotting of benchmark results
2020-01-31 14:39:41 +01:00
5a90a8b0dd
Merge pull request #117 from antmicro/init-fixes
...
phy/model: init fixes
2020-01-31 12:46:43 +01:00
8fa7a93e5c
phy/model: add support for sdram init for other memory types/widths
...
Up until now init worked correctly only on 32-bit SDR modules,
with this it should work at least with 64-bit wide DDR3, 128-bit DDR2
and 512-bit SDRAM
2020-01-31 11:14:32 +01:00
eacfbd8055
Merge pull request #122 from antmicro/jboc/benchmark
...
Load benchmark configuration from YAML
2020-01-30 16:08:30 +01:00
f6973aa9d7
test: load benchmark configurations from YAML file
2020-01-30 15:39:29 +01:00
090620c9d6
frontend/dma: add optional CSR control
2020-01-30 15:21:37 +01:00
096de78c63
test: fix `setup.py test` failing due to import error
...
because of relative import the script has to be run as:
python -m test.run_benchmarks
2020-01-30 14:11:52 +01:00
e17e6e34d8
Merge pull request #118 from antmicro/jboc/benchmark
...
Add a script for running LiteDRAM benchmarks
2020-01-30 13:31:11 +01:00
bb4f6106ee
test: print benchmarks summary
2020-01-30 10:50:08 +01:00
e822e6be9f
test: calculate benchmark bandwidth and efficiency
2020-01-30 10:19:17 +01:00
804a9b3727
test: add script for running multiple benchmarks and parsing results
2020-01-29 17:03:20 +01:00
a35a1f7790
Merge pull request #116 from antmicro/jboc/benchmark
...
test: add command line arguments for BIST base/length/random
2020-01-28 15:42:27 +01:00
502e6c663c
test: add command line arguments for BIST base/length/random
2020-01-28 15:03:36 +01:00
72e65e697f
Merge pull request #115 from antmicro/ddr4-model
...
phy/model: add burst_length value for ddr4 memories
2020-01-28 14:48:00 +01:00
cd25106fc1
phy/model: add burst_length value for ddr4 memories
2020-01-28 14:23:35 +01:00
6b91c1fa86
Merge pull request #111 from antmicro/write-latency
...
phy/model: simulate write latency
2020-01-28 14:05:16 +01:00
Mariusz Glebocki
Florent Kermarrec
Jędrzej Boczar
Piotr Binkowski