Florent Kermarrec
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090620c9d6
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frontend/dma: add optional CSR control
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2020-01-30 15:21:37 +01:00 |
Jędrzej Boczar
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096de78c63
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test: fix `setup.py test` failing due to import error
because of relative import the script has to be run as:
python -m test.run_benchmarks
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2020-01-30 14:11:52 +01:00 |
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enjoy-digital
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e17e6e34d8
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Merge pull request #118 from antmicro/jboc/benchmark
Add a script for running LiteDRAM benchmarks
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2020-01-30 13:31:11 +01:00 |
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Jędrzej Boczar
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bb4f6106ee
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test: print benchmarks summary
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2020-01-30 10:50:08 +01:00 |
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Jędrzej Boczar
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e822e6be9f
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test: calculate benchmark bandwidth and efficiency
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2020-01-30 10:19:17 +01:00 |
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Jędrzej Boczar
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804a9b3727
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test: add script for running multiple benchmarks and parsing results
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2020-01-29 17:03:20 +01:00 |
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enjoy-digital
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a35a1f7790
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Merge pull request #116 from antmicro/jboc/benchmark
test: add command line arguments for BIST base/length/random
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2020-01-28 15:42:27 +01:00 |
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Jędrzej Boczar
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502e6c663c
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test: add command line arguments for BIST base/length/random
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2020-01-28 15:03:36 +01:00 |
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enjoy-digital
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72e65e697f
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Merge pull request #115 from antmicro/ddr4-model
phy/model: add burst_length value for ddr4 memories
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2020-01-28 14:48:00 +01:00 |
Piotr Binkowski
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cd25106fc1
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phy/model: add burst_length value for ddr4 memories
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2020-01-28 14:23:35 +01:00 |
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enjoy-digital
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6b91c1fa86
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Merge pull request #111 from antmicro/write-latency
phy/model: simulate write latency
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2020-01-28 14:05:16 +01:00 |
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Piotr Binkowski
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f9d00f137b
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phy/model: simulate write latency
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2020-01-28 12:38:17 +01:00 |
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Florent Kermarrec
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586eb39b1d
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test: add initial benchmark test
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2020-01-28 12:07:22 +01:00 |
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Florent Kermarrec
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e4f901f070
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phy/model: review/simplify initialization
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2020-01-27 21:29:08 +01:00 |
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enjoy-digital
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9c00255483
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Merge pull request #104 from antmicro/phy-model-init
phy/model: add support for initializing memory from file
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2020-01-27 20:54:51 +01:00 |
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Florent Kermarrec
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e5e4f528d4
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examples/versa_ecp5.yml: enable CPU (required for DDR3 calibration), update copyright
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2020-01-27 18:30:24 +01:00 |
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Florent Kermarrec
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bb683a69ea
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litedram_gen: cleanup/rename CRGs, update copyrights
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2020-01-27 18:29:52 +01:00 |
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Florent Kermarrec
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4d19620a37
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litedram_gen: cleanup SDRAM PHY selection, remove plarform configuration parameter (can be deduced from PHY)
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2020-01-27 18:20:16 +01:00 |
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enjoy-digital
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b1f087959b
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Merge pull request #105 from ximinity/gen_ecp5
WIP: litedram_gen: add ecp5 support
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2020-01-27 17:50:47 +01:00 |
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Piotr Binkowski
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a3fc1b9219
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phy/model: add support for initializing memory from file
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2020-01-27 15:41:08 +01:00 |
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Florent Kermarrec
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74f72f91a0
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phy/usddrphy: reorder primitives parameters/signals
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2020-01-26 21:14:20 +01:00 |
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Florent Kermarrec
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11293dcccc
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phy/s7ddrphy: reorder primitives parameters/signals
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2020-01-26 21:00:57 +01:00 |
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Florent Kermarrec
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f252e8b27f
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phy/usddrphy: simplify dqs_serdes_pattern
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2020-01-26 12:55:14 +01:00 |
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Florent Kermarrec
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72da321fa4
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phy/usddrphy: cleanup primitives instances
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2020-01-26 12:44:48 +01:00 |
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Florent Kermarrec
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33c5d7b87e
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phy/s7ddrphy: simplify dqs_serdes_pattern
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2020-01-26 12:04:55 +01:00 |
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Florent Kermarrec
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2072ce77b0
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phy/s7ddrphy: cleanup primitives instances
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2020-01-26 12:00:14 +01:00 |
Stefan Schrijvers
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340a796129
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litedram_gen: add ecp5 support
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2020-01-25 18:59:26 +01:00 |
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Florent Kermarrec
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f4de17b8e6
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phy/ecp5ddrphy: reorder signals/parameters on primitives
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2020-01-25 17:00:18 +01:00 |
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Florent Kermarrec
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e0966e2ed3
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phy/ecp5ddrphy: improve presentation/readability
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2020-01-25 15:30:00 +01:00 |
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Florent Kermarrec
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bb1b431184
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test/test_init: use max_sdram_size of 1GB
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2020-01-24 10:46:29 +01:00 |
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Florent Kermarrec
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dc16d971ad
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modules: add M12L16161A
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2020-01-22 16:31:13 +01:00 |
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Florent Kermarrec
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ba9134a9a8
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litedram_gen: set min_l2_data_width to 0 (l2_data_width will use controller's data_width)
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2020-01-20 19:16:00 +01:00 |
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Florent Kermarrec
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cee3a43685
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modules: add M12L64322A
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2020-01-18 21:16:19 +01:00 |
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Florent Kermarrec
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6105ae371e
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modules: be sure tRFC use tuple on all modules
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2020-01-16 10:48:51 +01:00 |
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Florent Kermarrec
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2d40126e59
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litedram_gen: improve indent
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2020-01-16 10:47:15 +01:00 |
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Florent Kermarrec
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36e8ae9df1
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litedram_gen: remove underscore in AXI names to ease packaging
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2020-01-15 13:01:04 +01:00 |
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Florent Kermarrec
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61b19e2aaf
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litedram_gen: improve flexibility to define user ports
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2020-01-15 12:57:33 +01:00 |
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Florent Kermarrec
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76caff5417
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litedram_gen: add initial FIFO support
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2020-01-14 18:19:32 +01:00 |
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Florent Kermarrec
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7d13136cdb
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phy/model: small cleanup and add TODOs
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2020-01-14 11:17:23 +01:00 |
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Florent Kermarrec
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c07f4a1f1b
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gen: add l2_data_width to kwargs
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2020-01-13 17:31:17 +01:00 |
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Florent Kermarrec
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b77af48d50
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modules/H5TC4G63CFR: cleanup
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2020-01-13 17:05:46 +01:00 |
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enjoy-digital
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7d8287b57a
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Merge pull request #98 from Marrkson/master
ADD: KX2 DDR3 module
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2020-01-13 17:04:08 +01:00 |
Mark
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53887fcb8e
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ADD: KX2 DDR3 module
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2020-01-13 14:05:38 +01:00 |
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Florent Kermarrec
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6f35465c0b
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frotend/wishbone: avoid NextValue(count, 0) duplication
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2020-01-13 13:19:25 +01:00 |
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Florent Kermarrec
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721c84bad0
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frontend/wishbone: add efficient wishbone downconvert, improve DRAM access efficiency from CPU on boards with small native data_width.
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2020-01-13 12:58:15 +01:00 |
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Florent Kermarrec
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34e6c24d72
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frontend/wishbone: add write data buffer to avoid stalling wishbone while waiting for wdata.ready
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2020-01-10 14:27:05 +01:00 |
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Florent Kermarrec
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1d2bc922b8
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frontend/fifo: get back to original simple design and add test
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2020-01-07 15:40:09 +01:00 |
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Florent Kermarrec
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d1b603ae6c
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CONTRIBUTORS: update
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2020-01-07 09:46:54 +01:00 |
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Florent Kermarrec
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c858890213
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CONTRIBUTORS: update
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2020-01-07 09:45:36 +01:00 |
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enjoy-digital
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9523386e2c
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Merge pull request #97 from pdp7/master
add 32MB SDRAM for hadbadge
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2020-01-07 09:42:00 +01:00 |