fe48a9290c
test/reference: update.
2020-05-19 08:16:11 +02:00
c30910a9d2
init: generate DFII_CONTROL flags in sdram_phy.h instead of defining them in the BIOS.
2020-05-18 23:06:33 +02:00
5078b19bff
core/crossbar: remove retro-compat > 6 months old.
2020-05-18 18:51:56 +02:00
3b105d512b
modules: fix SDRAMRegisteredModule.
2020-05-15 21:39:00 +02:00
b2a5685396
Merge pull request #189 from daveshah1/ddr4_rdimm_init
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Add support for DDR4 RDIMMs
2020-05-15 21:34:43 +02:00
7ae4ad5b7d
modules: add SDR/DDR/DDR2/DDR3/DDR4 SDRAMModule (and Registered versions).
2020-05-15 21:27:43 +02:00
1f7d9eb0b9
litedram_gen: pass FPGA speedgrade to iodelay_pll.
2020-05-14 11:44:32 +02:00
22bd01c014
frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter
2020-05-13 17:14:42 +02:00
f4871b9f13
litedram_gen: use default settings on wb_bus.
2020-05-13 14:50:06 +02:00
b0bde294c0
frontend/wishbone: fix wb2native missing wdata.ready when wb/port data widths differ
2020-05-13 10:14:00 +02:00
6fb8396d8e
litedram_gen: remove csr_base (no longer needed since CPUNone type will automatically set csr mapping to 0x00000000) and create a use bus with the same address_width as the main bus of the SoC.
...
For some use cases, we will want to have the CPU + wb_ctrl interface.
2020-05-13 09:41:48 +02:00
79314f9549
frontend/wishbone: fix wdata.valid being high with old data, use cmd.last=1
2020-05-12 17:15:18 +02:00
000a352079
frontend/adaptation: delay sending write commands to prevent data loss during up-conversion
2020-05-12 17:15:18 +02:00
84fb7d338a
frontend/adaptation: refactor up-converter logic to use FSM for clarity
2020-05-12 17:14:58 +02:00
94c215e852
litedram_gen: review/simplify #193 , always add ddrctrl.
2020-05-12 16:21:04 +02:00
f036ec2c26
Merge pull request #193 from ozbenh/standalone-cores
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Improve standalone cores
2020-05-12 14:56:40 +02:00
04717b478b
gen: Rename standalone core wishbone
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Name it wb_ctrl rather than just wb, which makes the resulting
core signal names a bit more descriptive. IE. The DRAM control
bus (by opposition to the use/data buss(es).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:59:01 +10:00
b0838f70e3
gen: Add option to specify CSR alignment
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On some standalone core implementations, such with Microwatt,
the main system bus is 64-bit, but the wishbone to access the
CSRs is 32-bit.
To avoid extra logic & muxes and just wire these together, it's
useful to be able to specify a larger alignemnt (64-bit) for the
CSRs so that the generated csr.h contains the right offsets.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:58:13 +10:00
d5a03b3d89
gen: Add option to generate DDRCTL on standalone cores
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Microwatt will want that as it uses init_done to select whether
to run the SDRAM init code or the user code at reset.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:56:33 +10:00
efad6b3ca5
gen: Add option to specify CSR base for standalone cores
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:55:05 +10:00
c91cbb597d
gen: Remove obsolete bus_expose config option
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:54:47 +10:00
4e539ad76e
litedram_gen: switch to SoCCore.
2020-05-12 09:21:36 +02:00
ac33d29727
litedram_gen: simplify and expose bus when CPU is set to None.
2020-05-12 09:07:59 +02:00
fe478382e1
litedram_gen: expose a Bus Slave port instead of a CSR port.
...
The logic overhead is minimal and it makes things easier with more flexibility:
- since the main Bus is arbitrated, CPU and Bus Slave can coexist.
- integration is easier in LiteX.
- bridging to APB/AXI is easier.
2020-05-11 22:47:09 +02:00
efe9a44c93
frontend/adaptation: clean up LiteDRAMNativePortUpConverter code
2020-05-11 16:47:43 +02:00
2f35e9714d
frontend/adaptation: fix error when read follows write to the same address
2020-05-11 16:11:40 +02:00
1587ee3611
frontend/adaptation: use port.cmd.last instead of port.flush in up-converter
2020-05-11 15:28:32 +02:00
35fa91c055
test/crossbar: up-conversion with mode="both" should be working now
2020-05-11 14:56:39 +02:00
9b90a56e07
frontend/adaptation: combine read/write port up-converters and extend tests
2020-05-11 14:56:39 +02:00
762cd6d0f1
test/adaptation: add port converter tests with mode="both"
2020-05-11 14:56:39 +02:00
7a0f7a7ead
test/common: fix error in test data
2020-05-11 14:56:39 +02:00
1cc9656a2d
test/crossbar: improve NativePortDriver to use separate generatos on data paths
2020-05-11 14:25:06 +02:00
025e280804
test/crossbar: fix test that was not being run
2020-05-11 14:25:06 +02:00
52b49fb80e
test/reference: update.
2020-05-09 18:02:42 +02:00
52ca3936fe
modules: add MT41J512M16/MT41K512M16.
2020-05-09 16:37:24 +02:00
589957f115
phy: extend Bitslip capability to 2 sys_clk cycles.
2020-05-08 13:12:17 +02:00
5c0231d929
common/BitSlip: add cycles parameter to extend bitstlip to multiple system clock cycles.
2020-05-08 13:09:54 +02:00
ed0810a1af
gen: Optionally pass cpu_variant from YAML to SoC
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This allows the right gcc options to be set when using for
example VexRiscv_Min.v
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-06 21:42:37 +02:00
70054bacdb
Add support for DDR4 RDIMMs
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:34:41 +01:00
dfe6f90569
Merge pull request #188 from daveshah1/ddr4_dimm_x4
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usddrphy: Support for x4 chip based DIMMs
2020-04-29 12:03:10 +02:00
9f136c0fce
Merge pull request #187 from daveshah1/add_MTA18ASF2G72PZ
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modules: Add MTA18ASF2G72PZ DDR4 RDIMM
2020-04-29 12:01:52 +02:00
5b4381bcd3
usddrphy: Support for x4 chip based DIMMs
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 10:47:31 +01:00
97f0a3745b
modules: Add MTA18ASF2G72PZ DDR4 RDIMM
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 10:40:19 +01:00
9a2d3f0eb9
common: add PHYPadsReducer to only use specific DRAM modules.
...
For example on KC705, to only use the 4 first modules (bytes):
from litedram.common import PHYPadsReducer
ddram_pads = platform.request("ddram")
ddram_pads = PHYPadsReducer(ddram_pads, modules=[0, 1, 2, 3])
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(ddram_pads,
[...]
On Arty, to only use the second module (byte):
from litedram.common import PHYPadsReducer
ddram_pads = platform.request("ddram")
ddram_pads = PHYPadsReducer(ddram_pads, modules=[1])
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(ddram_pads,
[...]
2020-04-29 10:34:34 +02:00
20a849c652
test/reference: update ddr4_init.h
2020-04-28 11:57:11 +02:00
cec3a994e8
Merge pull request #181 from antmicro/jboc/eeprom-timings
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Add option to load module data from DDR3 SPD EEPROM
2020-04-25 08:25:35 +02:00
48c2fc2cad
phy: simplify/improve dqs preamble/postamble.
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Add some FIXMEs on ECP5DDRPHY.
2020-04-17 19:50:34 +02:00
312bce2bf1
modules: pass rate automatically when creating module from SPD data
2020-04-17 14:14:02 +02:00
07bbd79eaf
modules: update existsing SO-DIMM timings based on SPD data
2020-04-17 11:57:55 +02:00
eaf0691908
phy/ecp5ddrphy: simplify, working with dqs preamble/postamble.
2020-04-16 19:44:19 +02:00
Florent Kermarrec
Jędrzej Boczar
Benjamin Herrenschmidt
David Shah
Jędrzej Boczar