Commit Graph

18 Commits

Author SHA1 Message Date
Florent Kermarrec c2a779df46 bench: Update test targets (add_csr no longer required). 2021-04-19 13:40:17 +02:00
Florent Kermarrec 5cd192a708 bench: Remove soc_sdram import (No longer useful and deprecated). 2021-03-30 08:49:54 +02:00
Florent Kermarrec df5f555842 bench: Update with recent changes. 2021-03-12 10:25:11 +01:00
Florent Kermarrec c29c898af4 platforms/targets: switch to LiteX-Boards. 2021-01-04 14:11:32 +01:00
Florent Kermarrec a87c468afa bench: use --sys-clk-freq=xy to reconfigure frequency and fix Ultrascale. 2020-12-10 19:06:19 +01:00
Florent Kermarrec 75f87538a5 bench: use common load_bios function. 2020-12-10 11:21:21 +01:00
Florent Kermarrec ea63480253 bench/targets: add identifier. 2020-12-10 11:12:45 +01:00
Florent Kermarrec c472499131 bench/targets: add optional analyzer on all test targets. 2020-12-10 08:44:35 +01:00
Florent Kermarrec c83e10dafe bench: cleanup clocking on Ultrascale targets. 2020-11-06 16:14:22 +01:00
Florent Kermarrec 5cfdf77654 bench/targets: simplify BIST integration using new add_sdram with_bist parameter. 2020-11-06 10:34:26 +01:00
Florent Kermarrec a95c6883cc bench/targets: uniformize. 2020-10-29 18:58:37 +01:00
Florent Kermarrec 06544c6547 bench: uniformize targets with 125MHz clock and Etherbone. 2020-09-24 13:03:07 +02:00
Florent Kermarrec 7d0dac78c5 bench/kcu105: add a second pll to reduce frequency steps. 2020-08-28 19:03:44 +02:00
Florent Kermarrec 1fb78fa558 bench: cleanup, do more testing on 7-series. 2020-08-28 17:57:59 +02:00
Florent Kermarrec 248c5de517 bench: switch to UARTBone to simplify (and to allow testing boards without ethernet capability) and improve test. 2020-08-28 03:47:49 +02:00
Florent Kermarrec d3502e6a9b bench: add common.py with common bench test code. 2020-08-27 19:05:05 +02:00
Florent Kermarrec 2e3e19e9d4 bench: simplify/improve, working on arty/genesys2. 2020-08-27 18:41:54 +02:00
Florent Kermarrec 5c69da5d6d bench: add initial kcu105 bench target. 2020-08-24 21:56:11 +02:00