enjoy-digital
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cc7621df68
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Merge pull request #173 from antmicro/jboc/unit-tests
Add litedram.core.multiplexer tests
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2020-04-07 13:02:05 +02:00 |
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Florent Kermarrec
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e7cd6a7e2c
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.travis.yml: udpate to keep it similar with others .travis.yml files.
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2020-04-07 12:24:04 +02:00 |
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Florent Kermarrec
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0c3a610544
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setup.py: simplify, switch to Python3.6+ (using python_requires), remove version.
- Deprecate Python 3.5, switch to Python 3.6+.
- Remove which was not used or updated. We'll see to get this back when working on releases.
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2020-04-07 11:51:23 +02:00 |
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Florent Kermarrec
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a98f51e04e
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dfii: use reset_less on datapath/configuration CSRStorages.
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2020-04-06 13:17:47 +02:00 |
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Florent Kermarrec
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96b273c523
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common/BitSlip: use reset_less on intermediate signal.
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2020-04-06 11:59:34 +02:00 |
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Jędrzej Boczar
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a62e59bccf
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test: skip _CommandChooser tests from Issue #174
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2020-04-01 16:19:37 +02:00 |
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Jędrzej Boczar
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00fcdf6da7
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test: split core.multiplexer tests into separate files
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2020-04-01 15:36:14 +02:00 |
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Jędrzej Boczar
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f619bedda2
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test: clean up the code of core.multiplexer
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2020-04-01 15:03:30 +02:00 |
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Jędrzej Boczar
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1dd4227b34
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test: add core.multiplexer.Multiplexer tests
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2020-04-01 14:21:16 +02:00 |
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Jędrzej Boczar
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ea9324601c
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test: add comments to core.multiplexer._Steerer tests
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2020-03-30 16:00:20 +02:00 |
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Jędrzej Boczar
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26ce99320e
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test: add core.multiplexer._Steerer tests
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2020-03-30 13:16:03 +02:00 |
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Jędrzej Boczar
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f36b5a4fd2
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test: add core.multiplexer._CommandChooser tests
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2020-03-27 15:53:29 +01:00 |
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Jędrzej Boczar
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a1b1abe329
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test: use TestCase.subTest for more verbose error messages
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2020-03-27 15:42:13 +01:00 |
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enjoy-digital
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b06e946d09
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Merge pull request #172 from antmicro/zcu104-sodimm
modules: add MTA4ATF51264HZ DDR4 SO-DIMM
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2020-03-26 18:19:29 +01:00 |
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Florent Kermarrec
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f6babda683
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litedram_gen: fix LiteDRAMECP5DDRPHYCRG clkin freq (input_clk_freq and not sys_clk_freq).
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2020-03-26 18:10:26 +01:00 |
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Florent Kermarrec
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7fab898afc
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litedram_gen: use replace_in_file from litex, add comment on phy selection.
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2020-03-26 16:37:19 +01:00 |
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Florent Kermarrec
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d4d9ab740e
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litedram_gen/lattice: use trellis toolchain and LFE5UM5G-45F device for now.
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2020-03-26 16:32:58 +01:00 |
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Piotr Binkowski
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7238a9c0e2
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modules: add MTA4ATF51264HZ DDR4 SO-DIMM
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2020-03-26 16:18:16 +01:00 |
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Florent Kermarrec
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6951428af5
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test/test_fifo: minor cleanup.
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2020-03-26 12:23:25 +01:00 |
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Florent Kermarrec
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0ee9d7db5f
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test/test_ecc: review and cleanup.
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2020-03-26 12:00:08 +01:00 |
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Florent Kermarrec
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265e79f2aa
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test/gen_config: review/cleanup.
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2020-03-26 11:43:33 +01:00 |
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Florent Kermarrec
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2bb8f8fd22
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test/gen_access_pattern: cleanup.
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2020-03-26 11:03:43 +01:00 |
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Florent Kermarrec
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72d2bbf09d
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test/benchmarck: cleanup.
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2020-03-26 10:46:11 +01:00 |
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Florent Kermarrec
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0cbdbf18ad
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test/run_benchmarks: avoid relative imports as done on others tests.
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2020-03-26 10:17:02 +01:00 |
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enjoy-digital
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24c075ed3a
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Merge pull request #171 from antmicro/jboc/unit-tests-fifo
Add tests for litedram.frontend.fifo
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2020-03-26 09:40:17 +01:00 |
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enjoy-digital
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5919627a95
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Merge pull request #170 from antmicro/jboc/unit-tests
Add tests for litedram.frontend.adaptation
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2020-03-26 09:39:52 +01:00 |
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Jędrzej Boczar
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4fd6dc0ab6
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test: split test_fifo_ctrl into 2 separate tests
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2020-03-25 11:50:13 +01:00 |
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Jędrzej Boczar
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5d5bff3425
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test: add frontend.fifo tests
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2020-03-25 11:50:13 +01:00 |
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Jędrzej Boczar
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72b91a8fb7
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test: add timeout_generator
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2020-03-25 11:50:13 +01:00 |
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Florent Kermarrec
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043666672d
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phy/gensdrphy: sample rddata on sys_clk (assume clk generated to sdram is shifted), add cmd_latency parameter and simplify control logic.
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2020-03-24 19:50:35 +01:00 |
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Jędrzej Boczar
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c39a6bd059
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test: use @unittest.skip instead of commenting out code
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2020-03-24 14:35:28 +01:00 |
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Jędrzej Boczar
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0afacba2ca
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test: replace ConverterDUT.write_* with .write
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2020-03-24 12:04:53 +01:00 |
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Jędrzej Boczar
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7f36717516
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test: add LiteDRAMNativePortCDC tests
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2020-03-24 11:55:24 +01:00 |
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Jędrzej Boczar
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1f8868e6e9
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test: add frontend.adaptation tests for different conversion ratios
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2020-03-24 11:12:11 +01:00 |
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enjoy-digital
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ebdbcacc1d
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Merge pull request #169 from antmicro/jboc/unit-tests
Add LiteDRAMWishbone2Native tests
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2020-03-21 19:12:45 +01:00 |
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Florent Kermarrec
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d96dd94d55
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phy/s7ddrphy: add ISERDESE2 MEMORY mode support that uses DQS to sample the DQ datas.
This also reduces read latency by 1 sys_clk cycle.
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2020-03-20 18:54:23 +01:00 |
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Jędrzej Boczar
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f19d92b67f
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test: add wishbone tests with data width mismatch
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2020-03-20 14:48:50 +01:00 |
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Jędrzej Boczar
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7996ee5143
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test: add missing write-enable handling
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2020-03-20 14:48:50 +01:00 |
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Jędrzej Boczar
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3c0fdf0710
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test: handle 'we' in DRAMMemory, add memory debug messages
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2020-03-20 14:48:39 +01:00 |
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Jędrzej Boczar
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e8558f6f9f
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test: fix bits formatting
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2020-03-20 13:18:24 +01:00 |
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Jędrzej Boczar
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7593b2d9b9
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test: add basic wishbone test
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2020-03-20 09:30:33 +01:00 |
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enjoy-digital
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060d1807ad
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Merge pull request #168 from antmicro/jboc/unit-tests-ecc
Add unit tests for ECC
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2020-03-19 18:24:43 +01:00 |
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enjoy-digital
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4a784f083e
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Merge pull request #165 from antmicro/jboc/unit-tests
Test: add tests for BIST modules with different access patterns
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2020-03-19 18:24:00 +01:00 |
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Florent Kermarrec
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1c5e9408c8
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s6ddrphy/s7ddrphy: use IOBUFDS/IOBUF for DQS even if input is not currently used.
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2020-03-19 18:15:08 +01:00 |
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Jędrzej Boczar
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68d078cc78
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test: add tests for LiteDRAMNativePortECCW/LiteDRAMNativePortECCR
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2020-03-19 10:57:54 +01:00 |
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Jędrzej Boczar
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03f93998b5
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test: move DMA specific tests to test_dma.py
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2020-03-19 09:13:28 +01:00 |
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Jędrzej Boczar
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1b4647b2e1
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test: add tests for LiteDRAMNativePortECC
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2020-03-18 15:43:49 +01:00 |
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enjoy-digital
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d68eff02da
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Merge pull request #166 from Xiretza/standalone-builder-args
Allow specifying builder arguments for standalone generator
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2020-03-17 21:46:35 +01:00 |
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Xiretza
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ab4ce5d1af
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Allow specifying builder arguments for standalone generator
This is mostly copied over from liteeth.
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2020-03-17 20:02:18 +01:00 |
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Jędrzej Boczar
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36d5b42aa0
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test: correct DMAReaderDriver/DMAWriterDriver logic
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2020-03-17 15:37:50 +01:00 |
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