72d2bbf09d
test/benchmarck: cleanup.
2020-03-26 10:46:11 +01:00
0cbdbf18ad
test/run_benchmarks: avoid relative imports as done on others tests.
2020-03-26 10:17:02 +01:00
24c075ed3a
Merge pull request #171 from antmicro/jboc/unit-tests-fifo
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Add tests for litedram.frontend.fifo
2020-03-26 09:40:17 +01:00
5919627a95
Merge pull request #170 from antmicro/jboc/unit-tests
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Add tests for litedram.frontend.adaptation
2020-03-26 09:39:52 +01:00
4fd6dc0ab6
test: split test_fifo_ctrl into 2 separate tests
2020-03-25 11:50:13 +01:00
5d5bff3425
test: add frontend.fifo tests
2020-03-25 11:50:13 +01:00
72b91a8fb7
test: add timeout_generator
2020-03-25 11:50:13 +01:00
043666672d
phy/gensdrphy: sample rddata on sys_clk (assume clk generated to sdram is shifted), add cmd_latency parameter and simplify control logic.
2020-03-24 19:50:35 +01:00
c39a6bd059
test: use @unittest.skip instead of commenting out code
2020-03-24 14:35:28 +01:00
0afacba2ca
test: replace ConverterDUT.write_* with .write
2020-03-24 12:04:53 +01:00
7f36717516
test: add LiteDRAMNativePortCDC tests
2020-03-24 11:55:24 +01:00
1f8868e6e9
test: add frontend.adaptation tests for different conversion ratios
2020-03-24 11:12:11 +01:00
ebdbcacc1d
Merge pull request #169 from antmicro/jboc/unit-tests
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Add LiteDRAMWishbone2Native tests
2020-03-21 19:12:45 +01:00
d96dd94d55
phy/s7ddrphy: add ISERDESE2 MEMORY mode support that uses DQS to sample the DQ datas.
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This also reduces read latency by 1 sys_clk cycle.
2020-03-20 18:54:23 +01:00
f19d92b67f
test: add wishbone tests with data width mismatch
2020-03-20 14:48:50 +01:00
7996ee5143
test: add missing write-enable handling
2020-03-20 14:48:50 +01:00
3c0fdf0710
test: handle 'we' in DRAMMemory, add memory debug messages
2020-03-20 14:48:39 +01:00
e8558f6f9f
test: fix bits formatting
2020-03-20 13:18:24 +01:00
7593b2d9b9
test: add basic wishbone test
2020-03-20 09:30:33 +01:00
060d1807ad
Merge pull request #168 from antmicro/jboc/unit-tests-ecc
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Add unit tests for ECC
2020-03-19 18:24:43 +01:00
4a784f083e
Merge pull request #165 from antmicro/jboc/unit-tests
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Test: add tests for BIST modules with different access patterns
2020-03-19 18:24:00 +01:00
1c5e9408c8
s6ddrphy/s7ddrphy: use IOBUFDS/IOBUF for DQS even if input is not currently used.
2020-03-19 18:15:08 +01:00
68d078cc78
test: add tests for LiteDRAMNativePortECCW/LiteDRAMNativePortECCR
2020-03-19 10:57:54 +01:00
03f93998b5
test: move DMA specific tests to test_dma.py
2020-03-19 09:13:28 +01:00
1b4647b2e1
test: add tests for LiteDRAMNativePortECC
2020-03-18 15:43:49 +01:00
d68eff02da
Merge pull request #166 from Xiretza/standalone-builder-args
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Allow specifying builder arguments for standalone generator
2020-03-17 21:46:35 +01:00
ab4ce5d1af
Allow specifying builder arguments for standalone generator
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This is mostly copied over from liteeth.
2020-03-17 20:02:18 +01:00
36d5b42aa0
test: correct DMAReaderDriver/DMAWriterDriver logic
2020-03-17 15:37:50 +01:00
6ef623efae
test: cleanup test_bist.py code style
2020-03-17 14:23:08 +01:00
a883f88cca
test: add LiteDRAMDMAReader tests
2020-03-17 14:12:09 +01:00
d86ebd7e9d
test: add LiteDRAMDMAWriter tests
2020-03-17 12:39:10 +01:00
5618d2a54c
test: fix quotes
2020-03-17 09:45:28 +01:00
ef9b13d7e8
test: add tests for BIST modules with clock domain crossing
2020-03-16 16:38:58 +01:00
a00c8b7940
test: unify BIST tests, factor out repetitive code
2020-03-16 09:23:45 +01:00
13aeb3fd65
test: add _LiteDRAMBISTChecker/_LiteDRAMPatternChecker tests
2020-03-16 09:11:37 +01:00
ba83e5645c
test: add some more verbose _LiteDRAMBISTGenerator tests
2020-03-16 09:11:37 +01:00
239859d95b
test: add tests for _LiteDRAMPatternGenerator
2020-03-16 09:11:37 +01:00
ac06382b5a
test: split GenCheckDriver run into configure/run
2020-03-16 09:11:37 +01:00
4cfbc71fc2
Merge pull request #162 from antmicro/jboc/benchmark
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Benchmarks: fix with_uart parameter
2020-03-13 18:09:28 +01:00
c8423a08a3
test: exit with failure when no benchmarks succeeded
2020-03-12 14:16:21 +01:00
92daf53ea2
test: fix with_uart parameter (see litex/b29f443f)
2020-03-12 14:16:21 +01:00
60b618eeba
Merge pull request #161 from antmicro/jboc/unit-tests
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test: add _LiteDRAMBISTGenerator tests
2020-03-11 16:36:56 +01:00
cdde6bac19
Merge pull request #160 from antmicro/mglb/add-dqs
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common: PHYPadsCombiner: add "dqs" to the list
2020-03-11 16:23:53 +01:00
b89ecdf919
test: add _LiteDRAMBISTGenerator tests
2020-03-11 15:38:13 +01:00
a04b407c81
common: PHYPadsCombiner: add "dqs" to the list
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S6HalfRateDDRPHY uses "dqs" instead of "dqs_p"
2020-03-11 15:01:25 +01:00
6101eab3ac
phy/usddrphy: add assertions on iodelay_clk_freq.
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200MHz min on Ultrascale.
300MHz min on Ultrascale+.
2020-03-10 16:40:44 +01:00
052b436d9a
phy/usddrphy: add USPDDRPHY and rename sim_device parameter to device.
2020-03-10 16:07:53 +01:00
4ec676db27
modules: add MT40A512M8 DDR4.
2020-03-10 13:56:13 +01:00
183f1a6e27
phy/usddrphy: add cdly_value CSR to be able to read back configured clk/cmd delay.
2020-03-10 12:31:19 +01:00
26564ba93c
phys: integrate PHYPadsCombiner.
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pads can now be passed to the PHY as:
# DRAM Chips with common command/address lines (traditional):
pads = platform.request("ddram")
# DRAM Chips with dissociated command/address lines:
pads = [platform.request("ddram", 0), platform.request("ddram", 1)]
LiteDRAM controller will automatically adapts itself to this combined pads.
2020-03-06 18:56:28 +01:00
Florent Kermarrec
Jędrzej Boczar
Xiretza
Mariusz Glebocki