3897ed022c
Merge pull request #178 from FlyGoat/CPLLREFCLKSEL
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phy/usp_gth/gty_1000basex: Set proper CPLLREFCLKSEL
2024-12-18 11:30:50 +01:00
50ad88cc85
phy/usp_gth/gty_1000basex: Set proper CPLLREFCLKSEL for refclk_from_fabric
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As per Xilinx UG578 CPLLREFCLKSEL needs to be set to 111 when using GTGREFCLK
as clock source.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-12-16 15:50:58 +00:00
d2b1b0e0c5
frontend/stream: Add default ip_address/udp_port values.
2024-12-16 14:45:45 +01:00
aad9de7e53
frontend/stream/LiteEthStream2UDPTX: Add optional CSR to allow dynamic configuration (Enable, IP Address and UDP Port).
2024-12-13 21:27:47 +01:00
9f4d9d20bc
phy: Add initial Ultrascale+ GTYE4 10GBASE-R PHY.
2024-12-12 14:41:21 +01:00
0685079333
liteeth/phy/1000basex: Avoid splitting transceiver instance since no longer useful with current Python version.
2024-12-12 14:17:23 +01:00
99d4073c6a
phy/usp_gth/gty_1000basex: Add refclk_from_fabric parameter to allow selecting GTGREFCLK or GTREFCLK0.
2024-11-25 09:21:17 +01:00
17f80af672
liteeth/gen: Cosmetic cleanup in 1000BaseX.
2024-11-25 09:07:53 +01:00
1bbb735f9f
phy/pcs_1000basex: Cleanup PCSRX buffer and fix PCS TX ready on Start-of-packet.
2024-10-18 18:27:54 +02:00
a58e25c2f0
phy/pcs_1000basex: Remove rx_config_reg_ack.o check in AUTONEG-WAIT-ABI since no longer useful.
2024-10-18 14:23:14 +02:00
b783639889
phy/pcs_1000basex: Add specific breaklink timer and increase consistency count to 8.
2024-10-18 14:18:24 +02:00
20e9ea6656
phy/pcs_1000basex: Refactor/Simplify RX Config consistency check.
2024-10-16 11:28:45 +02:00
2a7df9cbba
phy/pcs_1000basex: Cleanup pass.
2024-10-16 10:44:40 +02:00
cd2274d905
phy/pcs1000basex: Improve/Simplify PCSRX source logic.
2024-10-16 10:33:39 +02:00
93472ef2d6
phy/pcs_1000basex/PCS: Another cleanup pass.
2024-10-15 21:51:27 +02:00
aa9c40988b
phy/pcs_1000basex: Add PCSSGMIITimer and share it between PCSTX/PCSRX.
2024-10-15 21:38:03 +02:00
fe69248ff3
phy/pcs_1000basex/PCS: Cleanup checker signal names, avoid ceil on timer values since this level of precision is not relevant.
2024-10-15 21:27:01 +02:00
01b91a3fd0
phy/pcs_1000basex: Replace PCSRX rx_en/data with stream.Endpoint and cosmetic cleanup.
2024-10-15 21:20:40 +02:00
9a123136e7
phy/pcs_1000basex: Update copyrights.
2024-10-15 12:56:25 +02:00
efcbebe558
Merge pull request #174 from enjoy-digital/1000basex_fixes_cleanup
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1000basex fixes cleanup.
2024-10-15 12:51:58 +02:00
16998377f6
phy/pcs_1000basex: Simplify/Cleanup PCSRX.
2024-10-15 12:50:39 +02:00
faf426f54a
phy/pcs_1000basex: Other cosmetic cleanup on PCSTX.
2024-10-15 11:46:39 +02:00
19e1d19444
phy/pcs_1000basex: Move PCS Gearbox.
2024-10-15 11:40:13 +02:00
313e7a985c
phy/pcs_1000basex: Simplify/Cleanup PCSTX.
2024-10-15 11:39:21 +02:00
8a3e0a23aa
phy/a7_1000basex: Use ALIGN_COMMA_WORD/RXCDR_CFG from Xilinx wizard.
2024-10-15 10:06:45 +02:00
04fc888285
liteeth/phy/pcs_1000basex: Avoid deadlock situation in AUTONEG_WAIT_ABI if receiving ACKNOWLEDGE instead of ABILITY.
2024-10-15 10:01:36 +02:00
e5746c8a81
phy/pcs_1000basex: Add missing RX Align during AUTONEG_WAIT_ABI state and enable/connect it on all PHYs.
2024-10-15 09:47:46 +02:00
7e602c406d
phy/pcs_1000basex: Replace self.lp_abi.o[0] with is_sgmii to ease understanding.
2024-10-15 09:28:09 +02:00
41c8b50ba5
phy/pcs_1000basex: Cleanup sgmii timer reload.
2024-10-15 09:26:34 +02:00
78b8f9ee85
mac/sram: Minor cosmetic cleanup.
2024-10-15 09:17:42 +02:00
f30d6ef7b9
mac/core: Switch to LiteXModule.
2024-09-27 15:14:23 +02:00
b96a6252c4
setup.py: 2024.08 release.
2024-09-27 09:35:27 +02:00
880bdf43b0
liteeth/phy/rmii: Add 10Mbps/100MBps dynamic speed support.
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Speed still needs to be changed manually, we could try to add automatic detection in the future.
2024-09-26 12:57:29 +02:00
7f91ebbee5
Merge pull request #172 from VOGL-electronic/phy_rmii_fix_efinix_sdr
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phy/rmii: fix it for efinix
2024-09-26 11:55:32 +02:00
90b1a18485
Merge pull request #173 from trabucayre/efinix_rework_clkinput_pll
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phy/trionrgmii,titaniumrgmii: replaces str by ClockSignal for ClkInput and PLL
2024-09-26 11:51:44 +02:00
3696ef82bb
phy/trionrgmii,titaniumrgmii: replaces str by ClockSignal for ClkInput and PLL
2024-09-26 11:03:12 +02:00
3693c61cbe
phy/rmii: fix it for efinix
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On efinix platforms the clk signal of
`SDROutput` and `SDRInput` has to come
from the PLL.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-25 17:06:29 +02:00
2b0156e9b3
liteeth/mac/core: Allow PHY to enforce with_preamble_crc/with_padding parameters.
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Avoid exposing these parameters up to add_ethernet since appropriate behaviour is generally
directly related to the type of PHY (ex LiteEthPHYModel or custom/specialized PHY).
2024-09-23 16:35:28 +02:00
1d19de09ef
phy/rmii: Cosmetic cleanups.
2024-09-23 15:30:08 +02:00
f252eed154
phy/rmii/LiteEthPHYRMIIRX: Avoid FSM, simplify and add comments.
2024-09-23 15:23:38 +02:00
5438ff01e1
phy/rmii/LiteEthPHYRMIIRX: Avoid reset on converter and improve frame delimitation.
2024-09-23 12:22:57 +02:00
66b277a80b
phy/rmii: Also use SDROutput on TX and add comments/simplify.
2024-09-23 11:53:42 +02:00
3cfbf007ab
phy/rmii/LiteEthPHYRMIIRX: Use SDRInput on pads.csr_dv/rx_data to make it clear input is synchronous.
2024-09-23 11:42:30 +02:00
5538c87115
liteeth/phy/rmii: Move crs first/last detection outside of FSM.
2024-09-23 11:30:57 +02:00
1c89387d09
liteeth/phy/rmii: Replace MuliReg with stream.Delay.
2024-09-23 11:05:23 +02:00
af746ec973
liteeth/core/__init__.py: Switch to LiteXModule.
2024-09-20 16:19:03 +02:00
a75f4e5ea7
CONTRIBUTORS: Update.
2024-09-20 12:28:14 +02:00
28cf1c267b
LICENSE/README.md: Bump year.
2024-09-20 12:27:07 +02:00
dd1988a40d
frontend/etherbone/LiteEthEtherbonePacketRX: Only enable LiteEthLastHandler for 64-bit case.
2024-09-20 12:15:18 +02:00
d5a9f9d2d4
core: Expose icmp_fifo_depth paramter.
2024-09-19 22:18:53 +02:00
enjoy-digital
Jiaxun Yang
Gwenhael Goavec-Merou
Fin Maaß