Florent Kermarrec
|
64cceb24b1
|
liteeth_gen: Expose reset.
|
2023-07-10 12:59:17 +02:00 |
Florent Kermarrec
|
7537dcb0fc
|
phy/100basex: Rename crg_reset to reset.
|
2023-07-10 12:58:55 +02:00 |
Florent Kermarrec
|
0d89c59c89
|
core/icmp/LiteEthICMPEcho: Verify packet length before storing in buffer and drop if too long for configurated depth.
|
2023-07-10 11:13:52 +02:00 |
Florent Kermarrec
|
31893a2d25
|
core/icmp: Add fifo_depth parameter.
|
2023-07-10 10:58:34 +02:00 |
Florent Kermarrec
|
01bdf0de07
|
frontend/etherbone: Switch to LiteXModule.
|
2023-07-10 10:37:00 +02:00 |
Florent Kermarrec
|
e7ea355959
|
core/udp: Switch to LiteXModule.
|
2023-07-10 10:24:56 +02:00 |
Florent Kermarrec
|
f3d08e589b
|
packet: Switch to LiteX/Module.
|
2023-07-10 10:24:37 +02:00 |
Florent Kermarrec
|
8a3534f84f
|
core/ip: Switch to LiteXModule.
|
2023-07-10 10:10:51 +02:00 |
Florent Kermarrec
|
f74beeeb71
|
core/icmp: Switch to LiteXModule.
|
2023-07-10 09:59:37 +02:00 |
Florent Kermarrec
|
01073323ff
|
core/arp: Switch to LiteXModule.
|
2023-07-10 09:57:54 +02:00 |
Florent Kermarrec
|
4bbb14a59c
|
crossbar: Switch to LiteXModule.
|
2023-07-10 09:53:45 +02:00 |
Florent Kermarrec
|
1be13c2ece
|
phy/pcs_1000basex: Switch to litex.gen.genlib.cdc.
|
2023-07-06 22:29:13 +02:00 |
Florent Kermarrec
|
e5168fe142
|
global: Switch to litex.gen.genlib.misc.
|
2023-07-06 22:06:37 +02:00 |
Florent Kermarrec
|
4954026a26
|
core/dhcp: Add Lumiguide to copyright.
|
2023-07-06 21:35:24 +02:00 |
Florent Kermarrec
|
5c806c150e
|
core/LiteEthUDP/IPCore: Use buffered TX/RX CDC as default since improving timing on low-end FPGAs and not impacting much resources.
|
2023-07-06 19:24:12 +02:00 |
Florent Kermarrec
|
70a89eafaa
|
core/dhcp: Add missing TX/RX reset on timeout.
|
2023-07-04 18:19:35 +02:00 |
Florent Kermarrec
|
d29d90cd78
|
liteeth_gen: Switch to LiteXModule and remove old TODO.
|
2023-07-03 19:15:12 +02:00 |
Florent Kermarrec
|
f8594ae429
|
phy/ecp5rgmii: Review/cleanup tx_clk addition.
|
2023-07-03 19:10:42 +02:00 |
Florent Kermarrec
|
8ae7649d03
|
liteeth: Review TX/RX CDC changes (cosmetic cleanups).
|
2023-07-03 19:04:58 +02:00 |
enjoy-digital
|
322d8625b5
|
Merge pull request #127 from rowanG077/master
Add core CDC depth and buffered parameters.
|
2023-07-03 18:57:24 +02:00 |
enjoy-digital
|
815c742c74
|
Merge branch 'master' into master
|
2023-07-03 18:55:44 +02:00 |
Florent Kermarrec
|
6bdc13bb07
|
README: Update.
|
2023-07-03 18:08:12 +02:00 |
Florent Kermarrec
|
f943a395f6
|
liteeth_gen: Add DHCP support and demonstrate it on udp_usp_gth_sgmii.yml config.
|
2023-07-03 18:07:36 +02:00 |
Florent Kermarrec
|
4afd325fc6
|
core/dhcp: Shorten offered_ip_address to ip_address.
|
2023-07-03 18:06:48 +02:00 |
Florent Kermarrec
|
7a988bee22
|
core: Add initial/minimal DHCP support to hardware stack.
Ex of use in a SoC that issues a DHCP request per second:
from liteeth.core.dhcp import LiteEthDHCP
from migen.genlib.misc import WaitTimer
# Signals.
ip_address = Signal(32)
mac_address = Signal(48, reset=0x10e2d5000001)
# Request Timer.
self.dhcp_timer = dhcp_timer = WaitTimer(int(sys_clk_freq/2))
self.comb += self.dhcp_timer.wait.eq(~self.dhcp_timer.done)
# DHCP.
dhcp_port = self.ethcore_etherbone.udp.crossbar.get_port(68, dw=32, cd="sys")
self.dhcp = dhcp = LiteEthDHCP(udp_port=dhcp_port, sys_clk_freq=sys_clk_freq)
self.comb += [
dhcp.start.eq(self.dhcp_timer.done),
dhcp.mac_address.eq(mac_address),
]
self.sync += [
If(dhcp.done,
ip_address.eq(dhcp.offered_ip_address)
)
]
|
2023-07-03 17:44:48 +02:00 |
Florent Kermarrec
|
ac4c2a7d44
|
liteeth/mac: Review/Minor changes to TXSlots write-only mode.
|
2023-07-03 10:50:07 +02:00 |
enjoy-digital
|
64627e3707
|
Merge pull request #135 from sensille/tx_write_only
Tx write only
|
2023-07-03 10:40:39 +02:00 |
Arne Jansen
|
53799444fd
|
Merge branch 'enjoy-digital:master' into tx_write_only
|
2023-06-28 18:50:48 +02:00 |
Florent Kermarrec
|
15054f6f8e
|
liteeth_gen/sgmii: Expose link_up status.
|
2023-06-28 11:09:19 +02:00 |
Florent Kermarrec
|
18cd5f234a
|
frontend/stream: Add 16-bit data-width support.
|
2023-06-28 11:02:37 +02:00 |
Arne Jansen
|
e83fd55fe8
|
add tx_write_only flag
This can save some resources in case reading the tx buffer is not needed.
It also makes it easier for synthesis to infer BRAM, tested on Spartan6.
|
2023-06-27 16:35:50 +02:00 |
Florent Kermarrec
|
65ef1930f5
|
liteeth_gen: Add refclk_freq parameter for SGMII/1000BaseX.
|
2023-06-23 12:51:15 +02:00 |
Florent Kermarrec
|
eab6b467f7
|
phy/usp_gtX_1000basex: Add 156.25MHz refclk_freq support in addition of 200MHz.
|
2023-06-23 12:43:35 +02:00 |
Florent Kermarrec
|
2dfd4398c9
|
phy/usp_gtX_1000basex: Use CPLLREFCLKSEL = 0b001 to let Vivado automatically select the right refclk.
|
2023-06-23 08:50:30 +02:00 |
Florent Kermarrec
|
2681a4f5d1
|
liteeth_gen: Finish adding Etherbone support.
|
2023-06-22 21:36:38 +02:00 |
Florent Kermarrec
|
52e94c02b5
|
liteeth_gen: Remove _eth suffix from PHY pads (not useful in case of a standalone core).
Will however require an update from design using the standalone core.
|
2023-06-22 17:31:01 +02:00 |
Florent Kermarrec
|
0d59ea180f
|
examples: Add udp usp gth sgmii example.
|
2023-06-22 16:50:24 +02:00 |
Florent Kermarrec
|
4650cb0a01
|
liteeth_gen: Add SGMII PHYs support (7-Series and Ultrascale+).
|
2023-06-22 16:49:15 +02:00 |
Florent Kermarrec
|
fc4003b115
|
liteth/phy: Update 1000basex imports and cleanup other imports.
|
2023-06-22 16:48:10 +02:00 |
Florent Kermarrec
|
9d22266233
|
frontend/stream: Update to LiteXModule and fix UDPTX packet send condition.
|
2023-06-14 11:17:37 +02:00 |
Florent Kermarrec
|
381ed30583
|
phy/k7_1000basex: Connect tx/rx_reset_done.
|
2023-06-13 19:18:29 +02:00 |
Florent Kermarrec
|
99d0fd92f3
|
phy/usp_gth_1000basex: Remove non-present/commented signals.
|
2023-06-13 19:13:40 +02:00 |
Florent Kermarrec
|
706f068822
|
phy/ku/usp_gth/gty_1000basex: Add rx/tx_polarity parameters for consistency with others 1000basex PHYs.
|
2023-06-13 19:12:04 +02:00 |
Florent Kermarrec
|
6c9dde1aca
|
phy/ku/usp_gth/gty_1000basex: Add with_csr parameter for consistency with other 1000basex PHYs.
|
2023-06-13 19:08:24 +02:00 |
Florent Kermarrec
|
3e026795d8
|
bench/xcu1525/xu8_st1: Directly add IOs in Etherbone section.
|
2023-06-13 18:36:15 +02:00 |
Florent Kermarrec
|
af5b9f433f
|
README: Add PHY support/family table.
|
2023-06-13 18:09:15 +02:00 |
Florent Kermarrec
|
9f69850697
|
usp_gth_1000basex: Working :), remove debug.
|
2023-06-13 17:44:12 +02:00 |
Florent Kermarrec
|
cfe3201854
|
phy/usp_gty_1000basex: Working :), remove debug.
|
2023-06-13 17:30:20 +02:00 |
Florent Kermarrec
|
bea94efae1
|
bench: Add Mercury XU8/ST1 bench to test/validate USP_GTH_1000BASEX.
|
2023-06-13 16:46:49 +02:00 |
Florent Kermarrec
|
d7aca70058
|
phy: Add initial usp_gth_1000basex (untested).
|
2023-06-13 16:41:26 +02:00 |