e2eb74f704
core/icmp: Simplify.
2021-09-22 18:36:03 +02:00
33322ad80f
core/arp: Simplify IDLE state.
2021-09-22 18:35:48 +02:00
4cadf912f2
bench/arty:bench/arty: Add UDP Streamer example with UDP TX stream from Switches.
2021-09-22 18:21:20 +02:00
c7aa4e50f4
frontend/stream/LiteEthStream2UDPTX: Fix/Simplify no FIFO case.
2021-09-22 18:05:59 +02:00
a26608f30f
bench/arty: Add UDP Streamer example with UDP RX stream redirected to Leds.
...
Tested with:
./arty.py --build --load
./test_udp_streamer.py --leds
2021-09-22 17:06:27 +02:00
a6298975bd
core/udp: Simplify LiteEthUDPTX.
2021-09-22 16:54:41 +02:00
8f05e72f99
frontend/etherbone: Simplify code.
2021-09-22 16:45:37 +02:00
bee34ee955
core/udp: Simplify LiteEthUDPRX and make sure to drop exceeding payload.
2021-09-22 16:32:47 +02:00
9b3837e636
Allow "device" to be specified in yaml
...
Otherwise we don't get the DDROutput overrides and the standalone
core fails to generate when using GMII_MII
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2021-09-22 22:27:30 +10:00
cccc0c720a
Add support for GMII_MII PHY to gen.py
...
It was missing. It's useful for Wukong
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2021-09-22 22:27:25 +10:00
393158f2a5
frontend/stream/LiteEthUDP2StreamRX: Pass last signal from Sink to Source.
2021-09-22 12:05:09 +02:00
9b88c0f299
frontend/stream: Apply convert_ip to ip_address.
2021-09-22 11:14:01 +02:00
27a0b99e54
common: Improve convert_ip to automatically detect passed format.
...
Simplify use in the code.
2021-09-22 11:13:33 +02:00
e39fec240b
CONTRIBUTORS: Update.
2021-09-15 14:49:06 +02:00
8e059b5124
phy/s6rgmii: Remove IBUF (ISE seems to have trouble with it).
2021-09-13 19:31:29 +02:00
109002985a
phy/gmii: add model parameter to skip clock buffers & generation
...
To support a simple GMII simulation, skip clock generation and buffer
logic. This allows to operate a GMII interface over sys_clk. Proper
GMII clocking support can still be added in the simulation, this
should work when setting model = False.
It also sets an attribute "model" such that we can avoid adding
Platform constraints in the rest of the ecosystem (such as
litex/litex/soc/integration/soc.py, add_ethernet and add_etherbone).
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-01 20:30:51 +02:00
c30abbdd60
mac/last_be: Adjust for dw≠8
...
In that case, last_be needs to be passed through
last_be also is now longer than 1
2021-08-18 13:54:12 +02:00
9b38fd8df3
mac/preamble: Fix inserter to work for 64 bit
...
On vivado at least
Co-authored-by: David Sawatzke <d-git@sawatzke.dev>
2021-08-17 19:23:35 +02:00
033d2a570b
mac/crc: Add 64 bit support to checker
2021-08-17 19:23:35 +02:00
eeee9a1173
mac/crc: Add 64 bit support to inserter
2021-08-17 19:23:35 +02:00
ea55332d26
Add 64-bit XGMII PHY implementation for 10G Ethernet
...
Adds support for 64-bit wide XGMII PHYs in LiteEth. A 64-bit wide
XGMII data path is a common method to interconnect multi-gigabit
Ethernet inside FPGAs. This module expects a 64-bit MAC data path,
which is to be added later. It has been tested locally using a
rewritten XGMII module for the LiteX simulator as well as on a KCU116
board.
This work has been inspired by enjoy-digital/liteeth#21 but is
entirely rewritten using Migen FSMs and with respect to
IEEE802.3-2018. Thanks to Florent Kermarrec (@enjoy-digital) and Vamsi
Vytla (@jersey99) for providing the base implementation.
This implementation does not yet support proper 32-bit (DDR) XGMII
PHYs, although support can be easily added by an additional module
which performs the DDR encoding / decoding of the data respectively.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-08-17 17:31:43 +02:00
fd827a545c
mac/crc: Simplify MACCRC32
...
Since only the reg of the widest engine is needed, the rest can be
removed
reverse_bits is also a bit more readable
The range for the engine data could be removed, but it's more
understandable this way
2021-08-12 18:38:06 +02:00
5d51806d6e
mac: Add endian converter if big endian for dw > 8
2021-08-12 18:38:06 +02:00
4119012b84
mac/core: Move gap into switchable domain & cleanup
2021-08-12 18:38:06 +02:00
ef214571d5
mac/core: Move preamble into switchable domain
2021-08-12 18:38:06 +02:00
688011f936
mac/preamble: Fix inserter to work for 32/64 bit
...
The signal won't get wider in the 8 bit case, since max moves from 6 to
7
Untested for 64 bit
2021-08-12 18:38:06 +02:00
8c72362385
mac/preamble: Add 32/64 bit support in checker
...
Only tested for 32/8 bit
2021-08-12 18:38:06 +02:00
811722cbaa
mac/core: Move crc into switchable domain
2021-08-12 18:38:06 +02:00
3f695a8320
mac/crc: Implement 32 bit support in inserter
2021-08-12 18:38:06 +02:00
03e847e90b
mac/crc: Implement 32 bit support in checker
2021-08-12 18:38:06 +02:00
7306c58ac8
mac/crc: Adjust crc generator/checker for last_be
...
Since the data can end at any sub-byte, just a 32 bit mac wouldn't work
2021-08-12 18:38:06 +02:00
8b8dae9fac
mac/core: Separate crc and premable block
...
So it can be more easily moved later on
2021-08-11 12:31:48 +02:00
be492e32de
mac/core: Add parameter to change processing domain
...
Per default, the processing should occur with sys_clk and dw, instead of
the phy parameters since it's not that much larger and allows for easier
timing requirements. But on some fpgas saving the few gates could be desirable
2021-08-11 12:31:44 +02:00
3e7979920a
mac/padding: Add 32 bit support to inserter
...
*Should* also work for 16/64 bit
2021-08-11 12:30:49 +02:00
0fb14d3c3f
mac/core: Extract data path converter into separate function
...
Allows it to be easily movable later on, as we move more into the sys
clk & dw path
2021-08-11 12:30:49 +02:00
c6c8be703b
Merge pull request #73 from antmicro/row-hammer
...
liteeth/phy: add configurable hw reset duration
2021-08-11 09:35:24 +02:00
a16bfdfc94
Merge pull request #72 from david-sawatzke/fullmemwe
...
mac: Allow configuring usage of FullMemoryWE (fixes #70 )
2021-08-11 09:34:34 +02:00
c3b9850366
liteeth/core: Allow configuration of full_mem_we parameter
2021-08-10 13:13:46 +02:00
e14c90dbc3
mac: Allow configuring usage of FullMemoryWE ( fixes #70 )
...
On ecp5 `FullMemoryWE` leads to an increase of DP16KD block mem, while
it works better on Intel/Altera devices according to
6c3af746e2
2021-08-10 13:13:46 +02:00
2a8cac96ba
Merge pull request #71 from antonblanchard/gen_tx_rx_slots
...
liteeth/gen: Allow configuration of nrxslots and ntxslots
2021-08-06 14:58:53 +02:00
7ac3fe681a
liteeth/gen: Allow configuration of nrxslots and ntxslots
...
We might want to increase nrxslots and ntxslots to improve
performance, so allow it to be overriden via the yaml config.
2021-08-06 06:09:49 +10:00
947ed03720
liteeth_gen: Allow configuring TX/RX delay RGMII PHYs.
2021-07-16 17:50:37 +02:00
72dd7bf283
mac/core/LiteEthMACCore: Switch CDC to ClockDomainCrossing and reduce buffering.
2021-07-16 14:51:25 +02:00
66fcad12cf
core/udp/get_port: Simplify code by letting CDC/Converter automatically simplify the logic when CDC/Converter are not required.
2021-07-15 19:53:17 +02:00
7ba5a59e12
core/arp/LiteEthARPTX: Move datapath outside of FSM (minor logic optimization).
2021-07-15 19:53:12 +02:00
a12d3991e5
core/icmp/LiteEthICMPTX: Move datapath outside of FSM (minor logic optimization).
2021-07-15 19:53:07 +02:00
43a2ea8118
frontend/Etherbone: Use new LiteX's PacketFIFO.
2021-07-15 18:07:15 +02:00
2b237881d9
core/icmp: Use new LiteX's PacketFIFO.
2021-07-15 18:06:52 +02:00
c294a3848e
bench: Add XCU1525 bench (compiles but not yet working on hardware).
2021-07-02 13:00:43 +02:00
2f4964cf56
phy: Add initial Ultrascale+ 1000BaseX PHY.
2021-07-02 12:59:00 +02:00
Florent Kermarrec
Benjamin Herrenschmidt
Leon Schuermann
David Sawatzke
Anton Blanchard