When no rx slot is available, the current code path sends the FSM through
DISCARD-REMAINING to TERMINATE, which tries to signal the slot to the user
even though nothing has been received. This can lead to data corruption.
TX packets are now sent when we have a full packet of when the FIFO is full.
Last can always be asserted from user-side when packet needs to be immediately
transmitted, the behavior will then be similar to previous implementation.
Errors are now also reported on RX.
Without setting the ref clock domain to None, generation failed:
Traceback (most recent call last):
File "/usr/lib/python3.10/site-packages/litex/gen/fhdl/verilog.py", line 535, in convert
f.clock_domains[cd_name]
File "/usr/lib/python3.10/site-packages/migen/fhdl/structure.py", line 741, in __getitem__
raise KeyError(key)
KeyError: 'eth'
During handling of the above exception, another exception occurred:
Traceback (most recent call last):
File "/usr/bin/liteeth_gen", line 33, in <module>
sys.exit(load_entry_point('liteeth==0.0.0', 'console_scripts', 'liteeth_gen')())
File "/usr/lib/python3.10/site-packages/liteeth/gen.py", line 389, in main
builder.build(build_name="liteeth_core")
File "/usr/lib/python3.10/site-packages/litex/soc/integration/builder.py", line 350, in build
vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
File "/usr/lib/python3.10/site-packages/litex/soc/integration/soc.py", line 1208, in build
return self.platform.build(self, *args, **kwargs)
File "/usr/lib/python3.10/site-packages/litex/build/xilinx/platform.py", line 73, in build
return self.toolchain.build(self, *args, **kwargs)
File "/usr/lib/python3.10/site-packages/litex/build/xilinx/vivado.py", line 349, in build
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
File "/usr/lib/python3.10/site-packages/litex/build/xilinx/platform.py", line 64, in get_verilog
return GenericPlatform.get_verilog(self, *args,
File "/usr/lib/python3.10/site-packages/litex/build/generic_platform.py", line 423, in get_verilog
return verilog.convert(fragment, platform=self, **kwargs)
File "/usr/lib/python3.10/site-packages/litex/gen/fhdl/verilog.py", line 541, in convert
raise Exception(msg)
Exception: Unresolved clock domain eth, availables:
- sys
- por
- eth_rx
- eth_tx
* in some cases, the delayed sink data was updated even though
sink was not valid, leading to corrupted source data
* this broke etherbone reads with DW=64
Pass through last_be or create a new one based on the length if needed
Initialize count at dw//8 and don't subtract source_length since it
could lead to underflow for very short packets. In case source.length is
not dw aligned, count will not be equal, so adjust comparison for that.
Crib last_be Case lookup from mac/sram.py
enjoy-digital
Arne Jansen
Victor Suarez Rovere
Xiretza
Michael Betz
Ilia Sergachev
David Sawatzke