291b257eb4
phy/crg: make rst_n optional on all PHYs and minor cleanup.
2020-11-23 16:24:44 +01:00
75495dd6ec
Merge pull request #54 from rprinz08/master
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Fix syntax and load error in Wireshark etherbone dissector
2020-11-23 13:44:57 +01:00
41b0f0c774
add initial bench directory with minimal arty/genesys2 test targets.
2020-11-23 13:40:54 +01:00
53057121e7
examples: remove old examples and update README (new benches/examples will be added).
2020-11-23 12:54:09 +01:00
5247a2008a
phy/ecp5rgmii: remove p_DEL_MODE (not required since we specify DEL_VALUE).
2020-11-23 12:16:07 +01:00
d3bbd506ba
Fix syntax and load error in Wireshark etherbone dissector
2020-11-07 10:55:21 +01:00
06242564f7
frontend/etherbone: simplify LiteEthEtherboneRecordReceiver.
2020-11-06 19:49:07 +01:00
d96fdfc5e5
frontend/etherbone: simplify LiteEthEtherboneRecordSender using combinatorial logic and fix #52 .
2020-11-06 19:43:57 +01:00
0c287d07f8
Merge pull request #51 from gregdavill/ecp5rgmii_delay_fix
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phy/ecp5rgmii: Fix io delay blocks
2020-10-12 09:17:02 +02:00
7fa06adf78
Merge pull request #48 from kbeckmann/fix_test
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test_etherbone: Fix import of etherbone module
2020-10-12 09:05:05 +02:00
317154f68f
Merge pull request #49 from gregdavill/ecp5_timing_fix
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mac/core: Improve timing closure of core
2020-10-12 09:04:34 +02:00
6ee11edb87
phy/ecp5rgmii: Fix io delay blocks
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For correct io delays in nextpnr the DEL_VALUE parameter needs to
be an integer, instead of the "DELAY{}" string.
The use of a "DELAY{}" string appears in the Lattice primitive
manual, but appears to be incorrect. At least based of the current
nextpnr.
Because we are not making use of dynamic io delays here we can
also use the simpler DELAYG block instead of DELAYF.
Fixes #50
2020-10-11 15:16:58 +10:30
9aee36939f
mac/core: Improve timing closure of core
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On ECP5 targets the core struggles to meet timing closure. This
change adds buffers to the CRC module on tx/rx paths.
This results in 20-30MHz gain to max clock rate.
This fixes #47
2020-10-11 14:46:16 +10:30
054eebc25f
test_etherbone: Fix import of etherbone module
2020-09-30 21:04:11 +02:00
54acf9fd76
phy/pcs_1000basex: keep up to date with MiSoC (adds SGMII and 10/100Mbps support).
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3768f5acc1
2020-08-24 22:14:35 +02:00
64b85e621e
add SPDX License identifier to header and specify file is part or LiteEth.
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Artix7/Ultrascale 1000BaseX is reused from MiSoC/LiteEthMini, specify it.
2020-08-23 16:07:12 +02:00
f275af8297
liteeth_gen: get Wishbone Platform's IOs with Interface.get_ios.
2020-08-22 21:22:02 +02:00
0705b35399
Merge pull request #46 from Xiretza/gen-py-wishbone
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Update gen.py to work with latest LiteX in wishbone mode
2020-08-22 21:16:22 +02:00
6a9a5132f6
Update gen.py to work with latest LiteX in wishbone mode
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Previously, it would fail with:
$ liteeth/gen.py examples/wishbone_mii.yml
[snip]
Traceback (most recent call last):
File "liteeth/gen.py", line 346, in <module>
main()
File "liteeth/gen.py", line 331, in main
soc = MACCore(platform, core_config)
File "liteeth/gen.py", line 244, in __init__
self.add_wb_master(bridge.wishbone)
File "[...]/litex/soc/integration/soc_core.py", line 202, in add_wb_master
self.bus.add_master(master=wbm)
File "[...]/litex/soc/integration/soc.py", line 347, in add_master
master = self.add_adapter(name, master, "m2s")
File "[...]/litex/soc/integration/soc.py", line 316, in add_adapter
bridge_cls = {
KeyError: (<class 'migen.genlib.record.Record'>, <class 'litex.soc.interconnect.wishbone.Interface'>)
2020-08-22 11:00:42 +02:00
792013a175
mac/sram: avoid asynchronous read port on LiteEthMACSRAMReader (fix the resource usage issue identified in #43 ).
2020-07-13 11:27:25 +02:00
1d76d02ea6
frontend: rename tty to stream (tty was too specific since modules can be used for any kind of data stream).
2020-07-13 10:08:50 +02:00
dbe15f17fc
Merge pull request #42 from shuffle2/padding
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mac padding: fix counter reset value
2020-06-26 15:43:07 +02:00
d66d302567
mac padding: fix counter reset value
2020-06-25 03:26:37 -07:00
b1bcfb2073
mac/LiteEthMACCoreCrossbar: remove unnecessary fifos.
2020-06-22 14:54:26 +02:00
8e1185711b
common: remove Port.connect and use 2 separate Record.connect.
2020-06-22 14:36:44 +02:00
17caf17c9e
mac/LiteEthMACCoreCrossbar: remove cpu_dw.
2020-06-19 22:06:53 +02:00
23b420a2dd
mac/LiteEthMAC: simplify hybrid mode and avoid some duplication.
2020-06-19 22:01:22 +02:00
51cd54602b
core/mac: add missing separators, fix typos.
2020-06-19 19:59:53 +02:00
59d3336bec
mac: add separators, improve indent, minor simplifications.
2020-06-19 19:42:25 +02:00
d06c7b49a2
frontend: add separators, improve indent, minor simplifications.
2020-06-19 19:21:24 +02:00
2d58f489ea
core: improve indent.
2020-06-19 19:12:12 +02:00
c26281882a
core: add separators.
2020-06-19 19:02:28 +02:00
bb29706e71
core: remove mac retro-compatibility (>6 months old).
2020-06-19 18:57:11 +02:00
0feed1720d
phy/gmii/CRG: add BUFG on RX and do the TX clock Mux with combinatorial logic (from @skiphansen initial work).
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This makes clocking more flexible and allows routing on more boards (ex: Pano Logic G2). Since TX clocking
does not need clock phase relationship with the input clock using a combinatorial path is fine.
2020-05-29 10:39:18 +02:00
53c9eb91a5
core/ip: move mcase_oui/ip_mask definition to common and set target_mac with NextValue.
2020-05-19 10:13:15 +02:00
58e1681f5d
Merge pull request #41 from shuffle2/mcast
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iptx: support multicast mac and bypass arp table
2020-05-19 09:51:11 +02:00
8afdec936d
phy/ecp5rgmii: review/simplify inband_status integration.
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For now keep it specific to ECP5, we'll integrate this soon on the others PHYs,
but some other refactoring/merging is required before.
2020-05-19 09:41:09 +02:00
55af430640
Merge pull request #40 from shuffle2/master
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ecp5rgmii: enable reading inband PHY_status
2020-05-19 08:36:59 +02:00
6d00ec1cc4
iptx: support multicast mac and bypass arp table
2020-05-17 14:52:02 -07:00
26c4e41b96
ecp5rgmii: enable reading inband PHY_status
2020-05-11 03:01:50 -07:00
dc67e6d070
phy/ecp5rgmii: use DDROutput/DDRInput now available for ECP5.
2020-04-22 10:14:36 +02:00
705003e523
README: switch to markdown.
2020-04-11 19:19:03 +02:00
92c30489ae
examples: use CRG from litex.build.
2020-04-10 10:31:14 +02:00
3bd807cf8f
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:20:41 +02:00
6ec7038b5b
.travis.yml: fix git clone error.
2020-04-07 12:16:37 +02:00
47a2e5b6fd
setup.py: simplify, switch to Python3.6+ (using python_requires), remove version.
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- Deprecate Python 3.5, switch to Python 3.6+.
- Remove which was not used or updated. We'll see to get this back when working on releases.
2020-04-07 11:54:31 +02:00
ab55304ab7
mac/sram: use reset_less on datapath/configuration CSRStorages.
2020-04-06 13:17:30 +02:00
fb478537e7
phy/gmii: use a BUFG between eth_rx.clk and eth_rx.clk.
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This makes it Xilinx specific, but without it ISE simplifies this as a single signal
(which is fine) but is not able to keep track of the "keep" attribute of both signals
and fails applying the constraints.
2020-03-25 12:40:02 +01:00
8accd6740a
Merge pull request #36 from antmicro/hybrid-mac
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mac: add crossbar for sharing PHY between HW ethernet cores and Wishbone
2020-03-19 22:09:57 +01:00
400ca97f45
examples: increase clk_freq to 125MHz on udp_s7phyrgmii.yml.
2020-03-19 22:01:33 +01:00
Florent Kermarrec
rprinz08
Greg Davill
Konrad Beckmann
Xiretza
Shawn Hoffman