Tim 'mithro' Ansell
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8b706ce05d
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Merge remote-tracking branch 'python-ignore/master' into gitignore
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2016-12-14 17:15:29 +01:00 |
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Tim Ansell
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13dad5a522
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GitHub's default .gitignore for Python.
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2016-12-14 17:11:37 +01:00 |
Florent Kermarrec
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edbcf65f6f
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software: some clean up and generate clk in dump
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2016-06-13 17:07:56 +02:00 |
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Florent Kermarrec
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b989ad6ce2
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setup.py: fix version (0.1)
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2016-04-29 14:41:47 +02:00 |
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Florent Kermarrec
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2877ead735
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core: remove rounding to next ceil_pow2 (not useful)
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2016-04-25 19:16:14 +02:00 |
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Florent Kermarrec
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9eb97d7879
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core/FrontendTrigger: remove (and wrong) dw computation
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2016-04-25 15:51:48 +02:00 |
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Florent Kermarrec
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b74bcb2fbf
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use new Record.connect omit parameter (replace leave_out)
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2016-04-21 08:06:24 +02:00 |
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Florent Kermarrec
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f8e3e63ef3
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fix cd_ratio support
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2016-04-03 22:58:12 +02:00 |
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Florent Kermarrec
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0c41c6a204
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core: minor fixes
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2016-04-03 18:26:50 +02:00 |
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Florent Kermarrec
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0f7f384ac9
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test: +x on scripts
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2016-04-03 17:30:58 +02:00 |
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Florent Kermarrec
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2539dce96f
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test/analyzer_tb: retrieve and print data
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2016-04-01 09:12:36 +02:00 |
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Florent Kermarrec
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b1b9e61ecf
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gateware: complete refactoring (only keep essential features, now less than 200 LOCs :)
use new LiteX features and only keep one trigger, subsampler, cdc, converter and storage modules.
software still needs to be cleaned up.
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2016-03-31 21:41:51 +02:00 |
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Florent Kermarrec
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e211d17ca6
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README: we are in 2016
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2016-03-31 00:07:27 +02:00 |
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Florent Kermarrec
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4f03da20ab
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frontend/logic_analyzer: add Converter for the cases where clk_domain frequency > system frequency
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2016-03-30 20:22:42 +02:00 |
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Florent Kermarrec
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97a0785e28
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common: remove direction in layout
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2016-03-30 20:21:21 +02:00 |
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Florent Kermarrec
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58a09bbdd6
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test: remove __init__.py and use setup.py develop
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2016-03-22 10:38:17 +01:00 |
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Florent Kermarrec
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8f88088f63
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global: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)
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2016-03-16 20:10:09 +01:00 |
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Florent Kermarrec
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7af786e47e
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example_designs: use new Vivado special overrides
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2016-03-16 19:48:38 +01:00 |
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Florent Kermarrec
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6d975fe388
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global: replace Sink/Source with stream.Endpoint
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2016-03-15 21:01:20 +01:00 |
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Florent Kermarrec
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88c4e2d126
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software/driver/logic_analyzer: fix case when config_csv is provided as a parameter
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2016-01-11 19:09:48 +01:00 |
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Florent Kermarrec
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83e06cad80
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example_designs: change the way we build cores (ensure consistent IO naming)
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2015-12-27 15:42:37 +01:00 |
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Florent Kermarrec
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378272d9e2
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some fixes (from refactoring)
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2015-12-27 13:14:53 +01:00 |
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Florent Kermarrec
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4bdd6813ef
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remove use of Record.connect
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2015-12-27 12:51:19 +01:00 |
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Florent Kermarrec
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8e7d89fc0c
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setup.py: exclude test directory
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2015-12-19 21:04:25 +01:00 |
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Florent Kermarrec
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21b76a1860
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example_designs/make.py: do not use "-" in build_name
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2015-12-12 16:51:35 +01:00 |
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Florent Kermarrec
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d0b4688184
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remove Counter module
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2015-11-24 21:50:01 +01:00 |
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Florent Kermarrec
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7b8169d8d2
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example_designs/test: fix test_logic_analyzer import
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2015-11-24 15:10:03 +01:00 |
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Florent Kermarrec
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92c7af04db
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example_designs/targets/core: use new Pins from LiteX (allow int parameters)
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2015-11-19 15:00:18 +01:00 |
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Florent Kermarrec
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577d83dc80
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test: use new RemoteClient/RemoveServer provided by LiteX
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2015-11-17 00:23:51 +01:00 |
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Florent Kermarrec
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198babae69
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stream/SyncFIFO now exposes fifo level
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2015-11-16 16:13:01 +01:00 |
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Florent Kermarrec
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553d7c5669
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update setup.py
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2015-11-14 17:31:14 +01:00 |
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Florent Kermarrec
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c4fcd17cce
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doc: remove skeleton and change logo (we'll add a better doc later)
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2015-11-14 01:13:01 +01:00 |
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Florent Kermarrec
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69ee0b76c0
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README: update
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2015-11-13 23:55:12 +01:00 |
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Florent Kermarrec
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24ef9d7ebe
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for now use our fork of migen
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2015-11-13 15:46:08 +01:00 |
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Florent Kermarrec
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947d974d0a
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start adapting to new migen/litex
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2015-11-12 01:04:28 +01:00 |
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Florent Kermarrec
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ce39265c0c
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use our own migen/misoc fork for now since migen/misoc is evolving
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2015-11-04 10:10:12 +01:00 |
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Florent Kermarrec
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edbdf1a864
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README: update
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2015-10-24 14:13:31 +02:00 |
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Florent Kermarrec
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9cc05dfe33
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example_designs/test/test_logic_analyzer: replace la with logic_analyzer
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2015-09-27 19:26:22 +02:00 |
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Florent Kermarrec
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19140a853b
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example_designs/test/Makefile: add clean
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2015-09-27 19:24:38 +02:00 |
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Florent Kermarrec
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7623739f5a
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change names of frontend modules: io --> inout, la--> logic_analyzer
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2015-09-27 18:47:30 +02:00 |
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Florent Kermarrec
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c436e160b6
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example_designs/test: add Makefile and test on de0nano
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2015-09-27 18:16:10 +02:00 |
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Florent Kermarrec
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d316948c87
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software/dump: cleanup imports
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2015-09-27 18:01:52 +02:00 |
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Florent Kermarrec
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34e8263572
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add dump_tb and cleanup dump code
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2015-09-27 17:47:07 +02:00 |
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Florent Kermarrec
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d4c4bb2c01
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example_designs: add core example
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2015-09-12 18:37:37 +02:00 |
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Florent Kermarrec
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820b444061
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test/Makefile: add example_designs to test regression on example_designs (only generate hdl)
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2015-09-12 16:54:25 +02:00 |
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Florent Kermarrec
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984feb185f
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litescope/common: add Counter (will be removed from migen)
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2015-09-12 16:53:59 +02:00 |
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Florent Kermarrec
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9393fee9f3
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init repo
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2015-09-09 08:24:08 +02:00 |