a255bc28ed
test: replace Makefile with test_examples, also integrate fast_scope_arty example
2019-11-23 11:16:32 +01:00
63c15167e1
example/fast_scope_arty: cleanup imports, remove program, allow disabling compilation by passing "no-compile"
2019-11-23 11:15:56 +01:00
bcd883ef8e
README: update
2019-11-22 19:47:46 +01:00
1f09678653
core: remove cd parameter retro-compatibility
2019-11-22 19:42:52 +01:00
c1b52f1887
core: cosmetic
2019-11-22 19:42:04 +01:00
c85c25bb78
add Travis-CI
2019-11-22 19:37:06 +01:00
5e7ee3555b
LICENSE/setup: update
2019-11-22 19:36:44 +01:00
6430dd09d0
test: update and add auto-check
2019-11-22 19:36:26 +01:00
bbc98b4404
core: remove reset on scope clk
2019-11-22 19:34:07 +01:00
1448b55819
examples: keep up to date with LiteX
2019-11-08 12:39:34 +01:00
7a9fa9d3b1
core: use new CSRStatus.we signal to speed-up Storage upload (>10x speedup over ethernet)
2019-09-24 18:03:06 +02:00
284253d558
core: add csr_csv parameter and export csv_csv on do_exit
2019-09-10 12:38:34 +02:00
69a8df013d
Merge pull request #14 from DurandA/master
...
Use cpu instead of cpu_or_bridge in examples
2019-08-20 14:40:01 +02:00
06cac3a142
Use cpu instead of cpu_or_bridge in examples
2019-08-20 13:55:00 +02:00
9e3b9d84ce
add CONTRIBUTORS file and add copyright header to all files.
2019-06-24 10:04:55 +02:00
66956cb88f
Merge pull request #13 from keesj/arty_fast_scope
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Arty fast scope
2019-06-24 09:32:10 +02:00
144bd06401
Add an example of sampling at 800Mhz using a serdes on arty.
2019-06-14 17:00:34 +02:00
7f4dc390d9
Add functionality to flatten values that are sampled using a serdes.
...
This code add some functionality to flatten the values back from
the serial to parallel conversion that happens when sampling
using the serdes.
2019-06-14 16:57:33 +02:00
2474ce9db2
software/dump/common: change variable name for values2x loop (thanks keesj)
2019-05-28 12:42:48 +02:00
7f20aa477f
examples/make/build-core: create build directory if not existing
2019-04-24 11:46:15 +02:00
c1d8bdf6f2
core: fix Trigger flush when disabled
2018-12-28 10:38:23 +01:00
1634fa35bb
test: use new RemoteClient import
2018-09-23 10:36:19 +02:00
cb27987b8c
examples/make: look for platform in migen if not present in litex
2018-09-21 07:52:29 +02:00
686db4f3cd
Merge pull request #12 from xobs/default-length
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analyzer-driver: use default depth from config
2018-09-13 14:38:56 +02:00
4f8b9a3567
analyzer-driver: use default depth from config
...
The configuration already knows what the default depth is, so just use
the default depth from there.
Also set the default offset to 0, since that is frequently a good default.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-09-13 13:48:09 +08:00
7c1c62e34a
README: update and rename example_designs to examples
2018-08-31 08:34:09 +02:00
3567b68981
dump/vcd: fix code generation
2018-08-30 14:39:09 +02:00
182b683586
core: change cd parameter to clock_domain (keep retro compatibility for now)
2018-08-28 11:58:44 +02:00
f26e36ef23
Merge pull request #11 from xobs/add-trigger-depth
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add trigger depth option
2018-08-02 10:49:50 +02:00
71ffaa7484
add trigger depth option
2018-08-02 11:01:44 +08:00
bfd06f819e
core: add FSM support (and example)
2018-07-20 09:36:42 +02:00
2ca58e488f
setup.py: fix exclude, add example_designs to exclude
2018-07-19 11:29:52 +02:00
cd63a43393
setup.py: exclude sim, test, doc directories
2018-07-18 09:43:23 +02:00
f03345d9f0
software/driver/analyzer: add get_instant_value to get instant value of one signal
2018-06-08 09:07:06 +02:00
af5bfd131f
software/driver/analyzer: add assertions
2018-06-04 10:10:03 +02:00
3efaefaae2
example_designs: typo
2018-06-04 08:04:10 +02:00
d919f90cf6
core: use bits_for(n) instead of max=n on Mux (fix case with only one group of signals)
2018-05-31 09:32:22 +02:00
6289e81b81
example_designs: demonstrate new features
2018-05-28 23:43:44 +02:00
e92f0b7ea2
example_designs/test: cleanup and simplify
2018-05-28 23:12:47 +02:00
2233bc290e
core: another cleanup/simplify pass
2018-05-28 23:12:15 +02:00
a269e67a10
software: add rising/falling edge support
2018-05-28 19:42:46 +02:00
65b7f08cbc
core: add full flag for trigger memory
2018-05-28 19:41:44 +02:00
c0bab06765
core: add sequential-triggering and simplify control
2018-05-28 19:16:53 +02:00
26a8b8989b
example_designs: update
2018-05-28 18:05:31 +02:00
8d4c1ddcf9
core: simplify and run storage in "scope" clock domain to get rid of cd_ratio.
2018-05-28 18:05:05 +02:00
9d5e605df3
replace litex.gen imports with migen imports
2018-02-23 13:43:47 +01:00
302a484697
bump to 0.2.dev
2018-02-23 13:43:28 +01:00
62c4bdd102
uniformize litex cores
2018-02-22 10:18:17 +01:00
985585f0b9
__init__: add LiteScopeIODriver and LiteScopeAnalyzerDriver imports
2018-02-19 14:50:03 +01:00
aa44da35c6
example_designs/make.py: fix typos
2018-01-20 21:22:28 +01:00
Florent Kermarrec
Arnaud Durand
kees.jongenburger
Sean Cross
bunnie