litex-boards/litex_boards/targets/terasic_de0nano.py

116 lines
4.5 KiB
Python
Raw Normal View History

2019-06-10 11:09:51 -04:00
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
2019-07-12 13:19:01 -04:00
import os
2019-06-10 11:09:51 -04:00
import argparse
from migen import *
2020-01-09 13:46:39 -05:00
from migen.genlib.resetsync import AsyncResetSynchronizer
2019-06-10 11:09:51 -04:00
from litex.build.io import DDROutput
from litex_boards.platforms import de0nano
2019-06-10 11:09:51 -04:00
from litex.soc.cores.clock import CycloneIVPLL
from litex.soc.integration.soc_core import *
2019-06-10 11:09:51 -04:00
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
2019-06-10 11:09:51 -04:00
from litedram.modules import IS42S16160
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
2019-06-10 11:09:51 -04:00
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
if sdram_rate == "1:2":
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
else:
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
2019-06-10 11:09:51 -04:00
# # #
2020-01-09 13:46:39 -05:00
# Clk / Rst
2019-06-10 11:09:51 -04:00
clk50 = platform.request("clk50")
2020-01-09 13:46:39 -05:00
# PLL
self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6")
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
if sdram_rate == "1:2":
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
else:
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
2020-01-09 13:46:39 -05:00
# SDRAM clock
sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
2019-06-10 11:09:51 -04:00
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), sdram_rate="1:1", with_led_chaser=True, **kwargs):
2019-06-10 11:09:51 -04:00
platform = de0nano.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on DE0-Nano",
ident_version = True,
**kwargs)
2019-06-10 11:09:51 -04:00
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
2019-06-10 11:09:51 -04:00
# SDR SDRAM --------------------------------------------------------------------------------
2019-06-10 11:09:51 -04:00
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = IS42S16160(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192)
)
2019-06-10 11:09:51 -04:00
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
2019-06-10 11:09:51 -04:00
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE0-Nano")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
2019-06-10 11:09:51 -04:00
builder_args(parser)
soc_core_args(parser)
2019-06-10 11:09:51 -04:00
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
sdram_rate = args.sdram_rate,
**soc_core_argdict(args)
)
2019-06-10 11:09:51 -04:00
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
2019-06-10 11:09:51 -04:00
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
2019-06-10 11:09:51 -04:00
if __name__ == "__main__":
main()