1631b071c3
finish up sdram, passes memtest
2020-01-30 03:41:44 -08:00
5091a1b40a
WIP sdram module option
2020-01-29 13:59:57 -08:00
3a6a9258ce
add de10 nano board
...
add iostandard to hdmi
2020-01-29 00:21:51 -08:00
e72cd1468c
platforms/ac701: fix eth indent
2020-01-18 21:34:50 +01:00
eca9bf10ae
mimas_v7: cleanup, make it similar to others boards
2020-01-16 11:24:09 +01:00
54f39b600a
mimas_a7: fix copyrights
2020-01-16 11:02:11 +01:00
8d298951a8
Merge pull request #37 from feliks-montez/master
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Add Mimas A7 board support
2020-01-16 11:00:32 +01:00
fd1e655700
targets: cleanup EthernetSoC
2020-01-16 10:28:09 +01:00
206ec34551
platforms/mimas_a7: add support
2020-01-14 23:31:03 -05:00
9f1c3305b6
targets/mimas_a7: add support
2020-01-14 23:30:49 -05:00
50d550c911
kx2: cleanup, fix copyright
2020-01-13 17:22:33 +01:00
3811b58f32
Merge pull request #36 from Marrkson/master
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ADD: KX2 and DDR3 support
2020-01-13 17:07:16 +01:00
c109b36fb9
travis: update/fix
2020-01-13 17:00:01 +01:00
028d4a78aa
targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args
2020-01-13 15:20:37 +01:00
13e5ca03a5
ADD: KX2 and DDR3 support
2020-01-13 14:21:54 +01:00
94ba343daf
targets/ac701: cpu_reset is active high
2020-01-10 18:53:14 +01:00
ab01f70e5c
platforms/ac701: set internal vref to 0.750v on DDR3 banks, use IN_TERM=UNTUNED_SPLIT_50 on dq
2020-01-09 21:56:01 +01:00
4192b20f09
targets: cleanup Altera CRGs
2020-01-09 19:46:39 +01:00
aaf8d54c6a
targets/de10lite: use AsyncResetSynchronizer for clock domains
...
At the start output of the pll is not stabilized, which
caused malfunctions when used for sys clock domain.
Use AsyncResetSynchronizer to start clock domains
on pll locked signal.
2020-01-09 18:47:13 +01:00
ab41cf5b79
Update ecp5_evn.py
2020-01-07 01:55:59 +01:00
2b43a18a3c
platforms/pipistrello: cleanup, remove extra stuff specific to litex-buildenv
2019-12-31 18:18:56 +01:00
c96e7c8fb9
platforms/pipistrello: cleanup, remove extra stuff specific to litex-buildenv
2019-12-31 18:07:18 +01:00
2259042383
pipistrello: add copyrights
2019-12-31 17:44:24 +01:00
6324433e1c
Merge pull request #28 from zakgi/master
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Adding initial support for Saanlima's Pipistrello LX45 board
2019-12-31 17:33:25 +01:00
980b0ebda0
targets/de10lite: rename VideoSoC to VGASoC (to avoid confusion with VideoSoC as used on Video designs with framebuffer)
2019-12-31 17:30:23 +01:00
10e5248bda
targets/de10lite: minor cleanup on import/_CRG
2019-12-31 17:26:09 +01:00
9c5a4f757f
targets/de10lite: add VideoSoC with VGA peripheral
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Add VideoSoC build option, based on Frank Buss example.
2019-12-30 23:25:43 +01:00
cace17e162
targets/de10lite: refactor setting up clock domains
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Use PLL to generate clock for both sys clock domain and clock domain
for sdram. Additionally set up clock domain for VGA periph.
2019-12-30 23:25:43 +01:00
9ed68d129f
platforms/de10lite: add additional configuration
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Use single image with memory initialization
to make more space for SoC ROM sector.
2019-12-30 23:23:44 +01:00
28753a2c04
platforms/de10lite: remove UART pins from GPIO resource
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V10 and W10 pins were used in UART periph, causing error
when gpio_0 were requested.
2019-12-30 23:06:58 +01:00
39e428581f
Adding initial support for Saanlima's Pipistrello LX45 board
2019-12-29 18:29:11 -08:00
30ea463b41
targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
2019-12-06 16:01:59 +01:00
f7fbfb4639
partner/community/targets: uniformize, improve presentation
2019-12-03 09:33:08 +01:00
2a0fbcadd2
ac701: add pcie_x1 pins
2019-11-06 09:29:55 +01:00
1ae26dd499
targets: use type="io" instead of io_region=True
2019-10-30 16:35:32 +01:00
785909ac5f
targets: switch from shadow_base to io_regions
2019-10-09 11:09:59 +02:00
b4eefa6c33
import: allow importing directly from litex_boards.platforms or litex_boards.targets
2019-09-03 15:30:20 +02:00
e704014b36
targets/__init__: comment targets import until we found a way to avoid litedram/liteeth dependecies for targets no using them.
2019-09-01 11:43:21 +02:00
f661ee0ec9
targets: fix import
2019-08-26 11:00:12 +02:00
ac58d57a83
targets: import platforms from litex_boards.platforms
2019-08-26 09:09:40 +02:00
b84308cb58
list all platforms/targets in platforms.py, targets.py to ease import
2019-08-26 09:07:07 +02:00
618f41bb1e
Update ecp5_evn.py
...
The system clock was driven directly while it should be driven by the PLL.
2019-08-22 02:27:50 +02:00
1abca7dcff
Turn litex_boards.community into module
2019-08-12 00:17:26 +02:00
ad21f15782
Merge pull request #10 from DurandA/ecp5-evn
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Add ECP5 Evaluation Board
2019-08-09 12:37:36 +02:00
c90950e319
Default to 60 Mhz system clock on ECP5 Evaluation Board
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Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.
2019-08-09 11:58:30 +02:00
9e6dccc277
Remove ECP5 Evaluation Board programmer
2019-08-09 11:54:49 +02:00
4126ed21d5
Add X5 clock and PLL to ECP5 Evaluation Board
2019-08-09 11:54:38 +02:00
c7444fe19c
Add ECP5 Evaluation Board
2019-08-09 09:45:13 +02:00
9f3ed82097
keep up to date with LiteX
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- use 1e9/freq for default_clk_period
- add default serial on tinyfpga_bx
- use S6PLL on minispartan6
- add SPIFlash pins on versa_ecp5
2019-08-07 08:47:08 +02:00
a88970a67f
move trellis board from community to partner
2019-07-12 19:23:21 +02:00
Paul Sajna
Florent Kermarrec
Feliks
Mark
Marcin Sloniewski
Arnaud Durand
Giammarco Zacheo