20720693c4
crosslink_nx_vip: Add HyperRAM support
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Signed-off-by: David Shah <dave@ds0.me>
2020-10-22 09:15:40 +01:00
b278d8bccc
Add CrossLink-NX VIP board platform and target
2020-10-22 09:15:35 +01:00
c3ea04b6e9
targets/s7/us: update sdram (manual cmd_latency no longer needed).
2020-10-12 18:46:21 +02:00
ddf7038c78
ulx3s: add 1.7 and 2.0 revisions support.
2020-10-12 13:23:26 +02:00
5e67853a21
versa_ecp5: Add --eth-phy to select ethernet phy
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This also simplifies the logic a bit.
2020-10-09 23:56:16 +02:00
477734ff06
versa_ecp5: Add etherbone support
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Etherbone can be enabled with --with-etherbone
2020-10-09 00:53:08 +02:00
fff20f7532
targets/fomu: base it on iCEBreaker target + USB-ACM.
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This uniformizes Fomu target with others, provide a simple example of LiteX SoC
on Fomu and will ease maintenance.
2020-10-06 11:39:30 +02:00
79ef091a06
Merge pull request #110 from pepijndevos/gowin
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Add initial support for Trenz TEC0117 board
2020-10-05 19:50:09 +02:00
062fbd6c63
Merge pull request #108 from daveshah1/dave/nx-evn-doc
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crosslink_nx_evn: Improve documentation on UART jumpers
2020-10-02 09:40:04 +02:00
18e5def9f2
don't verify erase, very slow
2020-10-01 08:41:16 +02:00
81e4f1f158
add initial support for Trenz TEC0117 board
2020-09-30 14:01:36 +02:00
de09b10726
targets/xcu1525: add ddram-channel selection and rewrite DRC workaround comment.
2020-09-24 18:19:49 +02:00
cc53206aff
targets/kcu105: create specific cd_eth for ethphy.
2020-09-24 10:25:55 +02:00
5b7288cfee
targets/kcu105: add Etherbone support.
2020-09-24 09:55:11 +02:00
77ba49f2bb
targets/pcie: update timing_constraints (now provided by the .xci).
2020-09-24 09:50:55 +02:00
e4cdbe0f7a
targets/ac701: reduce ddram pads to the first 4 modules.
2020-09-05 11:46:07 +02:00
8a9fd02768
crosslink_nx_evn: Improve documentation on UART jumpers
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Signed-off-by: David Shah <dave@ds0.me>
2020-09-05 09:58:28 +01:00
76ac4a69a8
rename forest_kitten_33 platform/target to fk33.
2020-09-04 20:05:18 +02:00
979fee7517
forest_kitten_33: add pcie.
2020-09-04 20:02:43 +02:00
ad48728160
xcu1525: update headers (were still using old format).
2020-09-04 19:59:09 +02:00
ad4c483c32
Merge pull request #106 from daveshah1/dave/alveo_u250_pcie
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alveo_u250: Add PCIe x4 support
2020-09-04 19:22:48 +02:00
a68c00e48e
Merge pull request #104 from DerFetzer/colorlight_5a_75e_v6_0
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Add support for 5A-75E V6.0 board
2020-09-04 19:21:02 +02:00
ae6a052e57
alveo_u250: Add PCIe x4 support
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Based on the implementation in xcu1525
Signed-off-by: David Shah <dave@ds0.me>
2020-09-04 14:20:04 +01:00
2eda9d0252
xcu1525: add DDR4 IOs for C1/C2/C3 and fix compilation (untested).
2020-09-04 11:34:33 +02:00
7b6b71d4e3
xcu1525: add initial DDR4 support in C0 (untested).
2020-09-03 19:48:23 +02:00
5a62a07b45
xcu1525: add initial PCIe support (untested).
2020-09-03 19:26:02 +02:00
51e881d1ff
add minimal xcu1525 support (VCU1525 or BCU1525 boards).
2020-09-03 19:06:43 +02:00
8bd736bd77
targets/colorlight_5a_75x: make Ethernet PHY selectable, cast sys_clk_freq to int for Wishbone
2020-09-02 22:08:45 +02:00
24b853c2db
targets/colorlight_5a_75x: force use of internal oscillator when using Ethernet with 5A-75E V6.0
2020-09-01 17:07:52 +02:00
8b1fee0e66
Add support for 5A-75E V6.0 board
2020-09-01 17:02:17 +02:00
9b6ed6bdf1
targets/orangecrab: add fallback to bootloader when usr_btn is pressed for 1 second.
2020-09-01 16:22:32 +02:00
b9ac72cf78
targets: simplify clocking on iCE40/ECP5 targets (AsyncResetSynchronizer now integrated in PLL).
2020-09-01 13:38:32 +02:00
9e2d301745
targets/icebreaker: simplify, update PLL/API and BIOS execution from SPI Flash.
2020-09-01 12:58:13 +02:00
beccecf59f
orangecrab: reduce DDR3 power consumption/heat and get back USB PLL to CRGSDRAM.
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- disable DQ termination.
- disable RTT_NOM.
- drive VCCIO/GND pads.
Reduce current from 0.25A to 0.12A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=48e6.
Still working at 96MHz, 0.17A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=96e6.
See https://github.com/enjoy-digital/litedram/issues/216 .
2020-08-28 20:01:54 +02:00
63b65e278c
crosslink_nx_evn: update copyrights.
2020-08-24 22:33:58 +02:00
153326fa26
targets/icebreaker: update flash.
2020-08-24 17:19:15 +02:00
795e34aafd
add initial Crosslink-NX support.
2020-08-24 16:47:38 +02:00
84c19a6cdf
targets/de0nano: set sys2x_ps phase to 180° for sdram_rate=1:2.
2020-08-24 09:28:51 +02:00
70594a5305
ulx3s: simplify sdram constraints and increase phase to 180 for sdram_rate=1:2.
2020-08-24 09:05:58 +02:00
1781be166a
general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
2020-08-23 15:00:17 +02:00
f328909578
Moved platform call inside of BaseSoC init for compatibility with linux-on-litex-vexriscv support. Added optional spi-sdcard support over P2 header.
2020-08-09 16:27:41 -04:00
45bb329b56
targets/colorlight_5a_75x: enable HalfRate SDRAM PHY.
2020-08-07 19:26:12 +02:00
b6a1ad5a9c
targets/orangecrab: add simple CRG when built without DDR3.
2020-08-07 18:10:03 +02:00
869ceadacb
targets: use platform.request_all on LedChaser.
2020-08-06 20:04:03 +02:00
ee28d7b5ec
targets/ulx3s/add_oled: simplify.
2020-08-04 12:31:15 +02:00
eba70377b7
add optional OLED peripheral to ULX3S target
2020-08-04 11:07:30 +02:00
5fd3e8dbcd
ecpix5: add SDCard.
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Validated with Linux-on-LiteX-VexRiscv.
2020-07-28 17:45:49 +02:00
94ccf1dd3e
targets/trellisboard: simplify clocking when no DDR3, remove firmware_ram (was here for debug).
2020-07-27 16:31:46 +02:00
eb8a484032
targets/de10nano: fix typo.
2020-07-26 12:01:11 +02:00
2cef54a909
targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required).
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This allows creating SoCs with CPU, SDRAM and Etherbone enabled all together.
2020-07-26 11:58:42 +02:00
David Shah
Florent Kermarrec
Konrad Beckmann
Pepijn de Vos
DerFetzer
Piense
connorwk