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Author SHA1 Message Date
Florent Kermarrec
ae47172d2a targets/decklink_mini_4k: Update clock constraints. 2022-11-14 10:21:42 +01:00
Florent Kermarrec
6e10df234f platforms/decklink_mini_4k: Fix data2_n pin (Thanks @rdolbeau). 2022-11-14 10:21:37 +01:00
enjoy-digital
169ce9e3d0
Merge pull request #450 from Icenowy/stlv7325-enh 
Some enhancements to STLV7325 target code
 2022-11-14 10:05:13 +01:00
Icenowy Zheng
e9d7013d70 sitlinv_stlv7325: add jtagbone support 
Add necessary script snippets for enabling jtagbone in the command line.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:28:04 +08:00
Icenowy Zheng
c2c59f5e8c sitlinv_stlv7325: allow to set local/remote ip 
Port the script snippet from Colorlight i5 for setting the local/remote
IP address to STLV7325.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:58 +08:00
Icenowy Zheng
3d8106f84d stlv7325: fix Ethernet IO voltages 
The IO voltages of Ethernet pins is set to 2.5V instead of 1.5V.

Fix this in the platform definition.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:23 +08:00
Icenowy Zheng
27c3afb8fb sitlinv_stlv7325: allow dynamic Ethernet IP 
Currently the sitlinv_stlv7325 target script parses the option that
selects dynamic Ethernet IP; however it's not really passed to LiteETH.

Really pass this option and add an assert that does not allow dynamic
Etherbone IP like other boards.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:23 +08:00
Icenowy Zheng
4ba5793822 sitlinv_stlv7325: remove unexistent COL/CRS pins 
The COL and CRS pins of the Ethernet PHY is not connected on the board
at all, but assigned dummy positions in the platform definition, which
leads to Vivado warning when building.

Remove these pins from the platform definition.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:23 +08:00
Icenowy Zheng
1c07fa94ca sitlinv_stlv7325: fix ident string vendor name 
As we changed the vendor name to proper Sitlinv in the file name, the
ident string is left untouched.

Fix this too.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:23 +08:00
Florent Kermarrec
58489ebebf targets/BaseSoC: Cleanup parameters. 2022-11-08 12:31:49 +01:00
Florent Kermarrec
a8c92cd86f targets/simple: Switch back to old version for now. 2022-11-08 11:55:06 +01:00
Florent Kermarrec
9e7079c4c8 targets: Remove int() on BaseSoC's sys_clk_freq. 2022-11-08 11:54:17 +01:00
Florent Kermarrec
b0e6414519 targets: Cleanup arguments and switch --sys-clk-freq to float (avoid conversion in code). 2022-11-08 10:41:35 +01:00
Florent Kermarrec
16b9677acd targets: Switch to soc_core_argdict. 
The next move was to remove soc_core and only keep soc; so this is probably the right time to do
it in targets to avoid having to handle it later.
 2022-11-07 08:43:26 +01:00
Florent Kermarrec
f1e24046fd xilinx_alveo_u250: Fix. 2022-11-06 22:17:28 +01:00
enjoy-digital
6edfb2ca7a
Merge pull request #448 from trabucayre/fix_alinx_axu2cga_platform 
platforms/alinx_axu2cga: adding missing psu_config at platform level
 2022-11-06 22:11:25 +01:00
Florent Kermarrec
9a2028a9ba targets: Remove useless argparse imports. 2022-11-06 22:09:21 +01:00
Florent Kermarrec
30723b1bb0 targets: Update targets that were still using argparse.ArgumentParser. 2022-11-06 22:07:17 +01:00
Gwenhael Goavec-Merou
24cd983b8c platforms/alinx_axu2cga: adding missing psu_config at platform level 2022-11-06 21:52:00 +01:00
Florent Kermarrec
33b0400aed targets: Update LiteXArgumentParser imports. 2022-11-06 21:39:52 +01:00
enjoy-digital
57f59409ac
Merge pull request #447 from trabucayre/rework_toolchain_args 
targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser
 2022-11-06 21:34:06 +01:00
Gwenhael Goavec-Merou
9960f38d95 targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser 2022-11-06 11:27:47 +01:00
enjoy-digital
61eb39101a
Merge pull request #445 from Icenowy/stlv 
stlv7325, a_e115fb: use the proper vendor name Sitlinv
 2022-10-30 09:50:30 +01:00
Icenowy Zheng
d7184fb043 stlv7325, a_e115fb: use the proper vendor name Sitlinv 
The boards are in fact from a vendor called 成都赛特凌威科技有限公司,
and their English registered trademark (used on the banner of their
Taobao store) is Sitlinv, which sounds like 赛特凌威.

Use this vendor name instead of where it's bought.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-10-30 10:51:13 +08:00
enjoy-digital
4dc8f7223c
Merge pull request #443 from trabucayre/arty_z7_bios 
targets/digilent_arty_z7: adding software support
 2022-10-28 10:42:35 +02:00
Florent Kermarrec
3e809c3a1e targets: Fix some LiteXModule imports. 2022-10-28 10:35:57 +02:00
Florent Kermarrec
ab3ed624cc fpgawars_alhambra2: +x. 2022-10-28 10:31:49 +02:00
enjoy-digital
20e65ce223
Merge pull request #442 from litex-hub/switch_to_litex_module 
targets: Switch to LiteXModule to simplify/cleanup code.
 2022-10-28 10:29:52 +02:00
Gwenhael Goavec-Merou
5f1b80fac4 targets/digilent_arty_z7: adding software support 2022-10-27 21:47:32 +02:00
Florent Kermarrec
548a028730 targets: Switch to LiteXModule to simplify/cleanup code. 2022-10-27 21:21:37 +02:00
enjoy-digital
6c05ddae1b
Merge pull request #438 from shawnanastasio/nexys4_part_name 
platforms/nexys4*: Update part name
 2022-10-27 12:11:07 +02:00
enjoy-digital
d863066942
Merge pull request #440 from jmrobles/main 
Add FPGAWars Alhambra II
 2022-10-27 09:29:14 +02:00
Chema
f9d3a39001 chore fix target, args processing 2022-10-26 20:45:53 +02:00
Chema
189ee3de39 fix target 2022-10-26 20:36:18 +02:00
Chema
54af30a4be fix: arg cpu-variant 2022-10-26 20:23:14 +02:00
Chema
32be05cfb1 chore default CPU variant 2022-10-25 21:14:25 +02:00
Chema
125569b2cb add FPGAWars Alhambra II 2022-10-25 21:12:02 +02:00
Florent Kermarrec
bd2f1c2553 targets/isx_im1283: Fix CI. 2022-10-22 16:23:50 +02:00
enjoy-digital
8e35f15c22
Merge pull request #437 from trabucayre/fix_redpitaya_mem_region 
targets/redpitaya: fix csr & reset region
 2022-10-22 16:00:22 +02:00
enjoy-digital
474dcb5fb3
Merge pull request #436 from Icenowy/isx-im1283 
Add ISX iM1283 board
 2022-10-22 15:56:43 +02:00
Shawn Anastasio
d4b2461b5a platforms/nexys4*: Update part name 
Symbiflow/f4pga don't recognize the part name xc7a100t-CSG324-1, so
change it to xc7a100tcsg324-1 which works with both f4pga and Vivado.
 2022-10-21 14:15:27 -05:00
Florent Kermarrec
5a8d846a86 targets: Remove add_csr calls (no longer required). 2022-10-21 08:42:24 +02:00
Florent Kermarrec
377cda05a3 ti60_f225_dev_kit: Switch 1.2V banks to 1.8V to fix compilation issues with latest Efinity. 
Will need to be investigated more.
 2022-10-20 18:21:52 +02:00
Gwenhael Goavec-Merou
4a5d5318d7 targets/redpitaya: fix csr & reset region 2022-10-20 16:35:57 +02:00
Florent Kermarrec
fbfd457ea0 ci: Bump to ubuntu 20.04. 2022-10-14 18:16:28 +02:00
Icenowy Zheng
745ebbbfa1 Add ISX iM1283 board 
ISX iM1283 is a "simple eDP signal generator" which utilizes a XC7A100T
FPGA, and come with a header populated with the FPGA's JTAG.

This commit adds initial reverse engineered IOs including the DDR3 DRAM
(which cannot work reliably @ DDR3-800, so the system clock is defaultly
set to 80MHz now), two LEDs and SD slot.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-10-14 22:50:43 +08:00
enjoy-digital
cb65099399
Merge pull request #435 from trabucayre/fix_artyz7_build 
targets/digilent_arty_z7: add flash region
 2022-10-14 15:49:52 +02:00
Florent Kermarrec
23c6acd013 platforms/ti60_f225_dev_kit: Fix IO voltage conflicts between peripherals/banks. 
Was already reported as a warning on 2021.1.165.2.19 but now an error with 2022.1.226.

Note: To get the build working with 2022.1.226 the following change had to be done to
pt/bin/writer/pinout.py, line 2254:
- table.add_rows(table_rows)
+ for table_row in table_rows:
+   table.add_row(table_row)
This would need to be investigated more to know if related to our local setup/machine.
 2022-10-14 10:22:54 +02:00
Gwenhael Goavec-Merou
e44e63f65d targets/digilent_arty_z7: add flash region 2022-10-13 19:48:41 +02:00
Florent Kermarrec
3b339ba9a3 platforms/xilinx_kc705: Fix flash proxy name. 2022-10-13 08:48:33 +02:00