d73bd2f7ce
targets/xilinx: add comment on sys_clk to pll.clkin false path.
2021-01-07 08:01:54 +01:00
1ac1c6857f
targets/xilinx: add false path constraint between sys_clk and pll.clkin.
...
The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.
2021-01-07 00:02:46 +01:00
d42af3ea19
targets: add --sys-clk-freq support to all targets.
2020-11-12 18:07:28 +01:00
72afb95329
targets: create platform on BaseSoC for all targets (consitency).
2020-11-12 16:57:31 +01:00
843e724e3d
targets/pcie: simplify using new LiteX's add_pcie method and enable it on all devices supported by LitePCIe.
2020-11-12 16:39:42 +01:00
7a9f175450
targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block.
2020-11-12 12:08:20 +01:00
4401fec1e6
targets: remove add_csr("crg") (no longer needed).
2020-11-12 11:54:11 +01:00
2b17dc1b89
target: add rst signal to CRG to allow full reset of the SoC on reboot command.
2020-11-04 11:13:42 +01:00
814e7630e4
targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
2020-10-13 12:10:29 +02:00
77ba49f2bb
targets/pcie: update timing_constraints (now provided by the .xci).
2020-09-24 09:50:55 +02:00
1781be166a
general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
2020-08-23 15:00:17 +02:00
fe3ea805bc
targets/pcie: make pcie optional (--with-pcie) and avoid forcing uart to crossover.
2020-06-30 18:44:00 +02:00
fc22e28fe9
targets: replace PCIeSoC with BaseSoC.
2020-06-30 17:41:57 +02:00
d28a0c4258
targets/pcie: remove DNA/XADC/ICAP that were only on PCIe targets.
...
DNA/XADC/ICAP are demonstrated in LitePCIe repository and should probably be added with
a add_xy method.
2020-06-30 17:37:24 +02:00
e91a5d6b82
targets/pcie: remove soft reset.
2020-06-30 17:28:13 +02:00
d87a11a9cb
targets/pcie: use generate_litepcie_software on all targets with PCIe.
2020-06-03 08:30:54 +02:00
eeba64d7b2
targets: use soc.build_name in load/flash bitstream.
2020-05-21 09:12:29 +02:00
482d7a6b95
targets/pcie: use 128-bit datapath and 8 max_pending_requests on pcie_x4 configurations.
2020-05-14 15:34:00 +02:00
27c242b2ca
targets/pcie: switch to PCIe X4 on all boards that support it.
2020-05-07 12:18:39 +02:00
f9939532b6
targets/pcie: update LitePCIe constraints.
2020-05-07 12:15:52 +02:00
2d9543b65e
targets: add build/load parameters on all targets.
2020-05-05 15:11:47 +02:00
84468c2a63
targets/CRG: platforms are now automatically constraining the input clocks.
2020-05-05 11:51:57 +02:00
4154bdf034
targets/PCIe: add PCIe software reset.
2020-04-20 12:30:09 +02:00
85f38876c2
targets: update PCIe on Numato targets.
...
Should be compatible with software from: https://github.com/enjoy-digital/netv2 .
2020-03-25 11:53:52 +01:00
83e6fb29f8
targets: switch to SoCCore/add_sdram instead of SoCSDRAM.
2020-03-21 12:43:39 +01:00
8211aca2e8
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
...
We initially wanted to provide different level of support for the platforms/targets, mainly
to avoid too much maintenance and let each contributor update its contributed platforms and
targets, but it's easier to update all platforms/targets all-together when LiteX evolves or
changes (and that's what has been done on litex-boards since the creation of the repository).
So let just simplify things and avoid this differentiation.
2020-02-03 09:36:30 +01:00
Florent Kermarrec