f400179b5b
targets: Import all from litex.gen on all targets.
2023-02-23 09:09:33 +01:00
9e7079c4c8
targets: Remove int() on BaseSoC's sys_clk_freq.
2022-11-08 11:54:17 +01:00
b0e6414519
targets: Cleanup arguments and switch --sys-clk-freq to float (avoid conversion in code).
2022-11-08 10:41:35 +01:00
16b9677acd
targets: Switch to soc_core_argdict.
...
The next move was to remove soc_core and only keep soc; so this is probably the right time to do
it in targets to avoid having to handle it later.
2022-11-07 08:43:26 +01:00
33b0400aed
targets: Update LiteXArgumentParser imports.
2022-11-06 21:39:52 +01:00
9960f38d95
targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser
2022-11-06 11:27:47 +01:00
548a028730
targets: Switch to LiteXModule to simplify/cleanup code.
2022-10-27 21:21:37 +02:00
45494f60e0
targets: Change SoC/Software headers generation behaviour (Now only generated with --build).
...
Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
2022-05-06 15:14:32 +02:00
a611f035d6
targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible.
...
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
2022-04-21 12:19:45 +02:00
9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
...
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
773444a7dd
targets: Switch to get_bios_filename/get_bitstream_filename.
2022-03-17 09:21:05 +01:00
fccb952c4b
target: Remove ident_version=True no longer required.
2022-01-18 17:13:02 +01:00
4b6a9b2cf0
targets/spiflash: Simplify self.cpu.set_reset_address call.
2022-01-07 15:19:23 +01:00
30cacc19c2
efinix_xyloni_dev_kit: Update SPI Flash.
2022-01-07 15:00:39 +01:00
53dc00eab7
targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description.
...
Also do minor adjustments while doing this.
2022-01-05 17:06:40 +01:00
8664b59f23
targets: Fix --bios-flash-offset support and other minor cleanups.
2021-12-20 21:41:12 +01:00
7ce8567d9b
targets/efinix: Bitstreams now directly generated to gateware directory.
2021-11-11 11:19:39 +01:00
c7a91f9eab
efinix: Enable identifier on SoC (issue fixed in LiteX).
2021-10-25 19:33:49 +02:00
4bcfde8882
efinix: Avoid no_we on ROM/RAMs (no longer required).
2021-10-25 19:10:03 +02:00
0ac0f9e75d
efinix_xyloni_dev_kit: Switch to openFPGALoader to load bitstream.
2021-10-25 12:49:48 +02:00
fc05379929
efinix_xyloni_dev_kit: Use PLL.
2021-10-25 12:16:47 +02:00
394ea23b99
efinix_xyloni_dev_kit: Only force variant to minimal for Vexriscv.
2021-10-22 14:47:12 +02:00
75fd276dbe
efinix_xyloni_dev_kit: Increase similarities with others boards and make target very similar to iceBreaker/Fomu/TangNano4k.
2021-10-21 11:34:55 +02:00
dc1328f1a5
efinix_xyloni_dev_kit: Fix copyrights.
2021-10-21 10:12:46 +02:00
c548b1c1e2
efinix: xyloni dev board basic support
...
* This works: efinix_xyloni_dev_kit.py --cpu-type None --build --load --flash
* issues with SPIflash - wrong generation for tristates miso mosi for
some reason
2021-10-19 11:23:29 +11:00
Florent Kermarrec
Gwenhael Goavec-Merou
Andrew Dennison