Florent Kermarrec
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75286f8a9b
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platforms/zcu104: add missing INTERNAL_VREF on bank 64 (DQ0-31)
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2020-03-10 14:57:39 +01:00 |
|
Florent Kermarrec
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95e1a05bf1
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platforms/Ultrascale: avoid unnecessary {{}} on INTERNAL_VREF.
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2020-03-09 09:29:49 +01:00 |
|
Florent Kermarrec
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3f191c8561
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mercury_xu5: set INTERNAL_VREF to 0.84. (similar to others Ultrascale boards with DDR4).
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2020-03-09 09:28:25 +01:00 |
|
Florent Kermarrec
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f4ae21a7a2
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zcu104: fix copyrights.
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2020-03-09 09:24:06 +01:00 |
|
Florent Kermarrec
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5031c11d57
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mercury_xu5: add missing copyrights.
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2020-03-09 09:23:08 +01:00 |
|
Florent Kermarrec
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8c535d15f2
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platforms/mercury_xu5: replace ' with ".
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2020-03-09 09:21:27 +01:00 |
|
enjoy-digital
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dc1371108d
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Merge pull request #52 from antmicro/jboc/mercury-xu5
add Enclustra Mercury XU5 board
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2020-03-09 09:11:15 +01:00 |
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Florent Kermarrec
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2b1b9684de
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targets/icebreaker: simplify CRG, just use a 12MHz sys_clk and por_clk for reset.
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2020-03-07 18:25:26 +01:00 |
|
Florent Kermarrec
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9416ddd84a
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targets/icebreaker: simplify arguments and make it closer to others targets.
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2020-03-07 18:13:02 +01:00 |
|
Florent Kermarrec
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992f7066fa
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targets/icebreaker: simplify leds.
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2020-03-07 18:12:59 +01:00 |
|
Florent Kermarrec
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682316214c
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targets/icebreaker: use specific method to set Yosys/Nextpnr settings. Rename argument to nextpnr-xxyy.
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2020-03-07 18:12:52 +01:00 |
|
Florent Kermarrec
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f777d4b08c
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targets/icebreaker: +x
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2020-03-05 23:11:35 +01:00 |
|
Florent Kermarrec
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6f517ad1d6
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targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
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2020-03-05 10:57:59 +01:00 |
Jędrzej Boczar
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d002059e0b
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add Enclustra Mercury XU5 board
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2020-03-05 10:52:32 +01:00 |
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enjoy-digital
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7776764580
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Merge pull request #51 from esden/icebreaker
Add iCEBreaker FPGA support
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2020-03-05 10:35:50 +01:00 |
Piotr Esden-Tempski
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745c99ba14
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icebreaker: Updated to build on newer litex. Disabled bios building.
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2020-03-05 00:12:18 -08:00 |
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Piotr Esden-Tempski
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3ac9d927a9
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targets: icebreaker: Minor style fixes.
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2020-03-05 00:12:18 -08:00 |
Sean Cross
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738967176c
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targets: icebreaker: set the boot address to point to SPI flash
Signed-off-by: Sean Cross <sean@xobs.io>
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2020-03-05 00:12:18 -08:00 |
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Sean Cross
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093e4913c4
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targets: icebreaker: hack to get boot working
Signed-off-by: Sean Cross <sean@xobs.io>
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2020-03-05 00:12:18 -08:00 |
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Sean Cross
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77b780eb4b
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targets: icebreaker: switch to single SPI
The Icebreaker doesn't have the QE/ bit set in config, so default to
using single SPI.
Signed-off-by: Sean Cross <sean@xobs.io>
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2020-03-05 00:12:18 -08:00 |
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Sean Cross
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e6dcdc31ed
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targets: icebreaker: fix cpu and add spi flash
Signed-off-by: Sean Cross <sean@xobs.io>
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2020-03-05 00:12:18 -08:00 |
|
Sean Cross
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0185095782
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targets: icebreaker: fix argument parsing for cpu
Signed-off-by: Sean Cross <sean@xobs.io>
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2020-03-05 00:12:18 -08:00 |
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Sean Cross
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f0dd31f6c8
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target: targets: add crg and begin getting it working
Signed-off-by: Sean Cross <sean@xobs.io>
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2020-03-05 00:12:18 -08:00 |
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Piotr Esden-Tempski
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ce9b67e2ee
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Added icebreaker platform and target.
Target is heavily based on Fomu.
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2020-03-05 00:12:18 -08:00 |
|
enjoy-digital
|
fd6c555117
|
Merge pull request #50 from TomKeddie/tomk_20200228_colorlight_connectors
platforms/colorlight_5a_75b: add J1-J8 connectors
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2020-02-28 19:11:30 +01:00 |
Tom Keddie
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7b4ca20ff4
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platforms.colorlight_5a_75b: add J1-J8 connectors
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2020-02-28 06:09:44 -08:00 |
|
Florent Kermarrec
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be5ed35871
|
targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).
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2020-02-28 09:46:54 +01:00 |
|
Florent Kermarrec
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b44885d222
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vc707: fix copyrights (Michael Betz is the initial author)
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2020-02-28 08:39:52 +01:00 |
|
Florent Kermarrec
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b89af28a05
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targets/kc705: use DDRPHY_CMD_DELAY to center write leveling.
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2020-02-27 12:58:52 +01:00 |
|
Florent Kermarrec
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edcc2cf63e
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test_targets: add vc707, zcu104, vcu118 and colorlight_5a_75b
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2020-02-27 11:17:28 +01:00 |
|
Florent Kermarrec
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aaa10c69eb
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platforms/colorlight_5a_75b: add default_clk_name/period
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2020-02-27 11:16:49 +01:00 |
|
Florent Kermarrec
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d8de4fbdfb
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platforms/targets: keep in sync with LiteX
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2020-02-27 11:06:53 +01:00 |
|
Florent Kermarrec
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18f65a7f9d
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platforms/kc705: cleanup ddram.
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2020-02-27 11:06:35 +01:00 |
|
Florent Kermarrec
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d4460c11a5
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platforms/kcu105/vcu118: remove PRE_EMPHASIS/EQUALIZATION on dm.
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2020-02-27 10:43:41 +01:00 |
|
Florent Kermarrec
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58f588f69e
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platforms/zcu104/ddram: add PRE_EMPHASIS/EQUALIZATION settings
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2020-02-27 10:43:01 +01:00 |
|
Florent Kermarrec
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d87b8b3c66
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zcu104: add separate ddram_32/64 definitions and use ddram_32 for now.
Ease switching between ddram_32 and ddram_64.
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2020-02-27 10:05:17 +01:00 |
|
Florent Kermarrec
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8ecfb13f3c
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zcu104: add copyrights
|
2020-02-27 09:57:26 +01:00 |
|
enjoy-digital
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22b0449509
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Merge pull request #47 from antmicro/zcu104
Add support for ZCU104 board
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2020-02-27 09:51:54 +01:00 |
Piotr Binkowski
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608541d5b8
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add ZCU104 board
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2020-02-26 13:53:21 +01:00 |
|
Florent Kermarrec
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e516ff3452
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vcu118/ddram: use similar IO settings than Xilinx's MIG, comment unused pins.
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2020-02-26 10:16:51 +01:00 |
|
Florent Kermarrec
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9d2ca50c5f
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kcu105/ddram: use similar IO settings than Xilinx's MIG, comment unused pins.
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2020-02-26 10:16:35 +01:00 |
|
Florent Kermarrec
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83d2c71099
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platforms/vcu118: add missing Internal Vref configuration on DDR4 C1/C2 banks
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2020-02-25 18:32:42 +01:00 |
|
Florent Kermarrec
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4a84e9b08a
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targets/colorlight_5a_75b: add instruction to build/load and use bitstream with wishbone-tool
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2020-02-25 12:47:08 +01:00 |
|
Florent Kermarrec
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f279fe9d33
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vc707: cleanup platform/targets, remove Ethernet support (no Ethernet pads defined)
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2020-02-25 10:35:18 +01:00 |
|
Florent Kermarrec
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3581df5af6
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vc707: cleanup platform/targets, remove Ethernet support (SGMII is not currently supported)
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2020-02-25 09:41:53 +01:00 |
|
Florent Kermarrec
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88a1f80db1
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vc707/vcu118: use proper copyrights
|
2020-02-25 09:03:52 +01:00 |
|
enjoy-digital
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e34654fc8c
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Merge pull request #46 from fei-g/master
add new board files for VC707 and VCU118
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2020-02-25 08:46:52 +01:00 |
Fei Gao
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373e74f435
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add new board files for VC707 and VCU118, only specified limited ports for VCU118, including clock, reset and DDR4
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2020-02-24 14:20:47 -05:00 |
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enjoy-digital
|
133f735e1f
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Merge pull request #45 from trabucayre/fix_colorlight5A-75B_SDRAM
platforms/colorlight_5a_75b.py: fix sdram_clock and sdram a pins
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2020-02-24 08:30:18 +01:00 |
Gwenhael Goavec-Merou
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2cf4e084ec
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platforms/colorlight_5a_75b.py: fix sdram_clock and sdram a pins
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2020-02-23 10:01:41 +01:00 |