9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
...
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
496b2cfab9
targets/gowin: Switch to get_bitstream_filename.
2022-03-17 09:40:10 +01:00
773444a7dd
targets: Switch to get_bios_filename/get_bitstream_filename.
2022-03-17 09:21:05 +01:00
fccb952c4b
target: Remove ident_version=True no longer required.
2022-01-18 17:13:02 +01:00
4b6a9b2cf0
targets/spiflash: Simplify self.cpu.set_reset_address call.
2022-01-07 15:19:23 +01:00
8151bf7ffa
targets: Update and simplify SPI-Flash support (Address is now automatically allocated).
2022-01-07 10:34:47 +01:00
53dc00eab7
targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description.
...
Also do minor adjustments while doing this.
2022-01-05 17:06:40 +01:00
8664b59f23
targets: Fix --bios-flash-offset support and other minor cleanups.
2021-12-20 21:41:12 +01:00
bf8b23c19f
trenz_tec0117: Update target.
2021-12-02 18:23:11 +01:00
1118b09350
trenz_tec0117: Switch to LiteSPI.
2021-07-28 10:34:17 +02:00
8c8e163eee
trenz_tec0117: Add SDCard (SPI and SD mode), move SPI Flash to 0x00000000 and use default l2_cache_min_data_width.
2021-07-20 17:25:51 +02:00
4b48f15265
Merge pull request #236 from JosephBushagour/jbushagour_with_led_chaser
...
Add with_led_chaser argument to constructor of boards using LedChaser submodule.
2021-07-16 14:41:05 +02:00
6648b2f907
targets/trenz_tec0117: Switch SPI Flash to QSPI mode.
2021-07-15 09:15:34 +02:00
c369f4bb7f
trenz_tec0117: Get BIOS XiP from SPI Flash working, remove CPU variant force since can now fit default VexRiscv config.
2021-07-14 12:49:03 +02:00
132feaf3e8
trenz_tec0117: Prepare for 1:2 SDRAM rate (Not yet working at 1:2 but one step closer...).
2021-07-14 10:43:26 +02:00
ba8321a3ab
trenz_tec0117: Use new DDROutput to generate SDRAM Clk.
2021-07-14 10:02:58 +02:00
94b985ac56
trenz_tec0117: Use new integrated reset from GW1NPLL.
2021-07-14 09:55:00 +02:00
6e31d12fa9
trenz_tec0117: Avoid forcing CPU type (only force to lite variant when VexRiscv is selected=default).
2021-07-13 19:39:53 +02:00
1920db3535
Add with_led_chaser argument to constructor of boards using LedChaser submodule.
2021-07-06 16:39:37 -05:00
2c5bf95f70
targets/trenz_tec0117: Switch to new GW1NPLL.
2021-04-30 11:32:24 +02:00
ba01776432
targets/add_sdram: Simplify call by removing useless arguments.
...
- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.
2021-03-29 15:28:31 +02:00
8a3cacae32
boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports).
2021-03-25 14:11:17 +01:00
Florent Kermarrec
Joey Bushagour