fcb83fa375
Merge pull request #621 from Philip-K/master
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Add support for S7 Mini (TE0890).
2024-11-16 18:40:34 +01:00
49c6c83378
Merge branch 'master' into ti375_c529
2024-11-16 18:39:17 +01:00
0e77cdf3c8
Merge pull request #616 from maass-hamburg/efinix_reset_pulse
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efinix: fix reset
2024-11-16 18:37:10 +01:00
a7d4422735
Add support for S7 Mini (TE0890).
2024-11-09 17:12:11 +01:00
15ad3ab341
platforms/limesdr_mini_v2.py: commented spiflash clk pad. Must be used via USRMCLK. Automatically done by LiteSPI
2024-11-09 07:20:51 +01:00
3b8c55802f
platforms/limesdr_mini_v2.py: fixed SPI Flash pinout MOSI <-> MISO
2024-11-06 16:58:11 +01:00
4c61bac2db
efinix_ti375_c529_dev_kit now support vexii ethernet
2024-11-01 09:33:42 +01:00
0eabebfb05
platforms/xilinx_zcu102.py: Add all SFP connectors
2024-10-10 07:34:57 +02:00
362a28b72a
efinix: fix reset
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fix reset on all efinix boards.
To reset the PLL a pulse is needed, which
has to be driven by a clock that is
not generated by the PLL.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-08 13:51:09 +02:00
399f10fdf9
add support for Mozart MX2
2024-10-05 08:16:18 +02:00
2d3a6b81e6
Add support for NetFPGA-Sume ( #604 )
2024-09-18 11:21:51 +02:00
1cfd32698c
Add support for Signaloid C0-microSD ( #601 )
2024-09-18 10:48:57 +02:00
4604379f46
platforms/sqrl_xcu1525: Revert previous commit, clk constraints were already present in DDR4 constraints.
2024-09-13 09:45:24 +02:00
90ff3d1ea9
platforms/sqrl_xcu1525.py: Add constraints on 300MHz clks.
2024-09-13 09:42:59 +02:00
1dbecf704d
efinix_ti375: Cosmetic cleanups on #610 .
2024-09-11 09:10:48 +02:00
d312ea331f
Merge pull request #610 from Dolu1990/ti375_c529
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Add efinix Ti375 c529 dev kit support
2024-09-11 08:18:44 +02:00
d209f64a45
Add efinix_ti375_c529_dev_kit support
2024-09-05 15:30:55 +02:00
b893374cdf
Fix ti60 dev kit spi-sdcard voltage
2024-09-05 15:28:07 +02:00
7f26f3940f
efinix_trion_t120_bga576_dev_kit.py: fixed/rewire rx_ctl/tx_ctl (not compatible with DDIO mode), added message at build time
2024-09-03 16:01:51 +02:00
664525471f
Got HDMI to work on hardware
2024-08-28 20:19:33 +02:00
5bfde29ce4
platforms/lattice_certuspro_nx_evn.py: fix led pinout
2024-08-28 17:02:05 +02:00
30e26cacac
Add sdcard and usb ohci support
2024-08-27 08:31:53 +02:00
144462e862
add jtag
2024-08-26 18:08:09 +02:00
e604745c7d
wip
2024-08-26 13:05:57 +02:00
0f8b8defb4
efinix ti375 c529 dev kit bios OK
2024-08-26 11:29:27 +02:00
4002b8167c
Merge pull request #602 from trabucayre/fix_tangPrimer20k_iostandard
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platforms/sipeed_tang_primer_20k.py: fix IOStandard values
2024-08-19 17:14:25 +02:00
52fc033bf5
Merge pull request #599 from trabucayre/sipeed_tang_gw5A_SDRAM
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Sipeed tang gw5 a sdram
2024-08-19 17:12:48 +02:00
a5ee3c807a
platforms/sipeed_tang_primer_20k.py: fix IOStandard values
2024-08-14 09:16:39 +02:00
b1a6da84b3
sipeed_tang_primer_25k: add SDRAM support (j3 connector), allows user to select between mister and sipeed SDRAM module
2024-08-04 12:14:56 +02:00
2fa838b79d
sipeed_tang_mega_138k_pro: added SDRAM sipeed variant, allows user to select between mister and sipeed SDRAM module, fix sipeed SDRAM memory module
2024-08-04 12:13:47 +02:00
241dfb6780
fix pinnumber on connector C
2024-08-01 19:14:49 +02:00
81209b9fd1
platforms/enclustra_mercury_xu8_pe3: Revert to VivadoProgrammer since OpenFPGALoader is not albe to load bitstream correctly if FPGA is not already configured.
2024-07-22 15:28:25 +02:00
ab732011b3
plaforms/lattice_certuspro_nx_xx: SPI_MASTER_PORT disabled (required to have access to the flash), added default clk period constraints
2024-07-22 14:49:03 +02:00
0394b626fa
platforms/enclustrat_mercury_xu8_pe3: Switch to OpenFPGALoader for loading FPGA.
2024-07-22 11:39:17 +02:00
6d3c87a6f7
platforms/lattice_certuspro_nx_versa: Fix default_clk.
2024-07-17 15:14:53 +02:00
fff2e6bd3f
platform: Add Lattice CertusPro-NX Versa initial support.
2024-07-17 14:53:12 +02:00
524387b45d
sqrl_xcu1525: Fix typo.
2024-07-11 12:54:38 +02:00
e94e84eb16
sqrl_xcu1525: Add more QSFP IOs.
2024-07-10 18:20:01 +02:00
c7b436a202
sqrl_xcu1525: Add QSFP-0/1 ref clks and rearrange a bit naming.
2024-07-10 17:04:48 +02:00
00df115e86
sqrl_xcu1525: Add QSFP-0/1 IOs.
2024-07-10 16:44:12 +02:00
5870b078f8
platforms/xilinx_vcu118: add fmc and pmod connector pinouts
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VCU118 board has one FMC HPC, one FMC+ HSPC and two PMOD connectors,
Vivado board files does not contain pinouts for these, so pinouts are
taken from VCU118 Evaluation Board User Guide (UG1224).
Signed-off-by: Yichuan Gao <gaoyichuan000@gmail.com>
2024-07-06 00:16:53 +08:00
15c6f89b1a
#570 : Update CAN support with LiteX https://github.com/enjoy-digital/litex/pull/2007 .
2024-07-05 10:26:28 +02:00
2e120bf8a4
Merge pull request #570 from disdi/master
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Add support for CTUCAN for Arty & Genesys2 board
2024-07-05 09:21:09 +02:00
7a157d787b
lattice_certus_prox_nx: Add missing OpenFPGAALoader import.
2024-07-01 15:58:31 +02:00
1c06988d80
platforms,targets/lattice_certuspro_nx_evn,lattice_certuspro_nx_vvml: set sysconfig SPI_MASTER mode by default at platform level
2024-07-01 11:07:25 +02:00
8579af5710
lattice_certuspro_nx_vvml: new board support
2024-06-28 12:47:57 +02:00
f27bbc9645
lattice_certuspro_nx_evn: new board support
2024-06-28 12:47:16 +02:00
bd58227c86
platforms/sqrl_acorn/_litex_acorn_baseboard_mini_io: Add SFP-I2C and Debug IOs.
2024-06-27 14:55:15 +02:00
91e787b5c3
platforms/sqrl_acorn: Add _litex_acorn_baseboard_mini_io for LiteX Acorn Baseboard Mini specific IOs.
2024-06-27 14:23:17 +02:00
75ef26b8e5
platforms/machdyne_mozart_mx1.py: adding default_clk_name, default_clk_period (fix CI failure)
2024-06-22 22:43:06 +02:00
enjoy-digital
Phil Kirkpatrick
Gwenhael Goavec-Merou
Gwenhael Goavec-Merou
Dolu1990
Fin Maaß
inc
Gustav
Apostolos - Nikolaos Vailakis
Malte
Yichuan Gao