2013-05-07 04:30:56 -04:00
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from mibuild.generic_platform import *
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2015-03-29 06:15:39 -04:00
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from mibuild.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer, iMPACT
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2015-03-13 18:17:45 -04:00
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from mibuild.xilinx.ise import XilinxISEToolchain
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2013-05-07 04:30:56 -04:00
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_io = [
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("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
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("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")),
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("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")),
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("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")),
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("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")),
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("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")),
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("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")),
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("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
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2014-10-17 05:08:37 -04:00
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2013-05-07 04:30:56 -04:00
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("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")),
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2014-10-17 05:08:37 -04:00
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2013-05-07 04:30:56 -04:00
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("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")),
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("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")),
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("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")),
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("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")),
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("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")),
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2014-10-17 05:08:37 -04:00
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2013-05-07 04:30:56 -04:00
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("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")),
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("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")),
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("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")),
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("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")),
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2014-10-17 05:08:37 -04:00
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2015-02-26 18:22:22 -05:00
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("user_sma_clock", 0,
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Subsignal("p", Pins("L25"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("K25"), IOStandard("LVDS_25"))
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),
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2013-05-07 04:30:56 -04:00
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("clk200", 0,
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Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
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Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
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),
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2014-10-17 05:08:37 -04:00
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2013-05-07 04:30:56 -04:00
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("clk156", 0,
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Subsignal("p", Pins("K28"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("K29"), IOStandard("LVDS_25"))
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),
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2014-10-17 05:08:37 -04:00
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2013-05-07 04:30:56 -04:00
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("i2c", 0,
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Subsignal("scl", Pins("K21")),
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Subsignal("sda", Pins("L21")),
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IOStandard("LVCMOS25")),
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2014-10-17 05:08:37 -04:00
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2013-05-07 04:30:56 -04:00
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("serial", 0,
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Subsignal("cts", Pins("L27")),
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Subsignal("rts", Pins("K23")),
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Subsignal("tx", Pins("K24")),
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Subsignal("rx", Pins("M19")),
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IOStandard("LVCMOS25")),
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2014-08-21 07:34:30 -04:00
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("spiflash", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("U19")),
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Subsignal("dq", Pins("P24", "R25", "R20", "R21")),
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IOStandard("LVCMOS25")
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),
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2013-05-07 04:30:56 -04:00
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("mmc", 0,
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Subsignal("wp", Pins("Y21")),
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Subsignal("det", Pins("AA21")),
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Subsignal("cmd", Pins("AB22")),
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Subsignal("clk", Pins("AB23")),
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2013-06-25 16:57:31 -04:00
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Subsignal("dat", Pins("AC20 AA23 AA22 AC21")),
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2013-05-07 04:30:56 -04:00
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IOStandard("LVCMOS25")),
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2014-10-17 05:08:37 -04:00
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2013-05-07 04:30:56 -04:00
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("lcd", 0,
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2013-06-25 16:57:31 -04:00
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Subsignal("db", Pins("AA13 AA10 AA11 Y10")),
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2013-05-07 04:30:56 -04:00
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Subsignal("e", Pins("AB10")),
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Subsignal("rs", Pins("Y11")),
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Subsignal("rw", Pins("AB13")),
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IOStandard("LVCMOS15")),
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2014-10-17 05:08:37 -04:00
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2013-05-07 04:30:56 -04:00
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("rotary", 0,
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Subsignal("a", Pins("Y26")),
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Subsignal("b", Pins("Y25")),
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Subsignal("push", Pins("AA26")),
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IOStandard("LVCMOS25")),
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2014-10-17 05:08:37 -04:00
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2013-05-07 04:30:56 -04:00
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("hdmi", 0,
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2013-06-25 16:57:31 -04:00
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Subsignal("d", Pins("B23 A23 E23 D23 F25 E25 E24 D24 F26 E26 G23 G24 J19 H19 L17 L18 K19 K20")),
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2013-05-07 04:30:56 -04:00
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Subsignal("de", Pins("H17")),
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Subsignal("clk", Pins("K18")),
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Subsignal("vsync", Pins("H20")),
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Subsignal("hsync", Pins("J18")),
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Subsignal("int", Pins("AH24")),
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Subsignal("spdif", Pins("J17")),
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Subsignal("spdif_out", Pins("G20")),
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IOStandard("LVCMOS25")),
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2014-07-28 05:54:50 -04:00
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("ddram", 0,
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2014-07-29 22:31:26 -04:00
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Subsignal("a", Pins(
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"AH12 AG13 AG12 AF12 AJ12 AJ13 AJ14 AH14",
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"AK13 AK14 AF13 AE13 AJ11 AH11 AK10 AK11"),
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2014-07-28 05:54:50 -04:00
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IOStandard("SSTL15")),
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2014-07-29 22:31:26 -04:00
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Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")),
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2014-08-08 22:56:59 -04:00
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Subsignal("cs_n", Pins("AC12"), IOStandard("SSTL15")),
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2014-07-28 05:54:50 -04:00
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Subsignal("dm", Pins("Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"),
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IOStandard("SSTL15")),
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2014-07-29 22:31:26 -04:00
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Subsignal("dq", Pins(
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"AA15 AA16 AC14 AD14 AA17 AB15 AE15 Y15",
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"AB19 AD16 AC19 AD17 AA18 AB18 AE18 AD18",
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"AG19 AK19 AG18 AF18 AH19 AJ19 AE19 AD19",
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"AK16 AJ17 AG15 AF15 AH17 AG14 AH15 AK15",
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"AK8 AK6 AG7 AF7 AF8 AK4 AJ8 AJ6",
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"AH5 AH6 AJ2 AH2 AH4 AJ4 AK1 AJ1",
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"AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5",
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"AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"),
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2014-09-01 17:11:40 -04:00
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IOStandard("SSTL15_T_DCI")),
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2014-07-28 05:54:50 -04:00
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Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("AG10"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("AH10"), IOStandard("DIFF_SSTL15")),
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2014-08-08 22:56:59 -04:00
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Subsignal("cke", Pins("AF10"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("AD8"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("AK3"), IOStandard("LVCMOS15")),
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2014-07-28 05:54:50 -04:00
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Misc("SLEW=FAST"),
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Misc("VCCAUX_IO=HIGH")
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),
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2014-10-31 07:49:30 -04:00
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("eth_clocks", 0,
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Subsignal("tx", Pins("M28")),
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Subsignal("gtx", Pins("K30")),
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Subsignal("rx", Pins("U27")),
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IOStandard("LVCMOS25")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("L20")),
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Subsignal("int_n", Pins("N30")),
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Subsignal("mdio", Pins("J21")),
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Subsignal("mdc", Pins("R23")),
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Subsignal("dv", Pins("R28")),
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Subsignal("rx_er", Pins("V26")),
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Subsignal("rx_data", Pins("U30 U25 T25 U28 R19 T27 T26 T28")),
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Subsignal("tx_en", Pins("M27")),
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Subsignal("tx_er", Pins("N29")),
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Subsignal("tx_data", Pins("N27 N25 M29 L28 J26 K26 L30 J28")),
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Subsignal("col", Pins("W19")),
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Subsignal("crs", Pins("R30")),
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IOStandard("LVCMOS25")
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),
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2013-05-07 04:30:56 -04:00
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]
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2015-02-18 10:32:43 -05:00
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_connectors = [
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("HPC",
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{
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"DP1_M2C_P": "D6",
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"DP1_M2C_N": "D5",
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"DP2_M2C_P": "B6",
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"DP2_M2C_N": "B5",
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"DP3_M2C_P": "A8",
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"DP3_M2C_N": "A7",
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"DP1_C2M_P": "C4",
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"DP1_C2M_N": "C3",
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"DP2_C2M_P": "B2",
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"DP2_C2M_N": "B1",
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"DP3_C2M_P": "A4",
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"DP3_C2M_N": "A3",
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"DP0_C2M_P": "D2",
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"DP0_C2M_N": "D1",
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"DP0_M2C_P": "E4",
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"DP0_M2C_N": "E3",
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"LA06_P": "H30",
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"LA06_N": "G30",
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"LA10_P": "D29",
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"LA10_N": "C30",
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"LA14_P": "B28",
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"LA14_N": "A28",
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"LA18_CC_P": "F21",
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"LA18_CC_N": "E21",
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"LA27_P": "C19",
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"LA27_N": "B19",
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"HA01_CC_P": "H14",
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"HA01_CC_N": "G14",
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"HA05_P": "F15",
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"HA05_N": "E16",
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"HA09_P": "F12",
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"HA09_N": "E13",
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"HA13_P": "L16",
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"HA13_N": "K16",
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"HA16_P": "L15",
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"HA16_N": "K15",
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"HA20_P": "K13",
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"HA20_N": "J13",
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"CLK1_M2C_P": "D17",
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"CLK1_M2C_N": "D18",
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"LA00_CC_P": "C25",
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"LA00_CC_N": "B25",
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"LA03_P": "H26",
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"LA03_N": "H27",
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"LA08_P": "E29",
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"LA08_N": "E30",
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"LA12_P": "C29",
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"LA12_N": "B29",
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"LA16_P": "B27",
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"LA16_N": "A27",
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"LA20_P": "E19",
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"LA20_N": "D19",
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"LA22_P": "C20",
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"LA22_N": "B20",
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"LA25_P": "G17",
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"LA25_N": "F17",
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"LA29_P": "C17",
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"LA29_N": "B17",
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"LA31_P": "G22",
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"LA31_N": "F22",
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"LA33_P": "H21",
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"LA33_N": "H22",
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"HA03_P": "C12",
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"HA03_N": "B12",
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"HA07_P": "B14",
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"HA07_N": "A15",
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"HA11_P": "B13",
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"HA11_N": "A13",
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"HA14_P": "J16",
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"HA14_N": "H16",
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"HA18_P": "K14",
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"HA18_N": "J14",
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"HA22_P": "L11",
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"HA22_N": "K11",
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"GBTCLK1_M2C_P": "E8",
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"GBTCLK1_M2C_N": "E7",
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"GBTCLK0_M2C_P": "C8",
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"GBTCLK0_M2C_N": "C7",
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"LA01_CC_P": "D26",
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"LA01_CC_N": "C26",
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"LA05_P": "G29",
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"LA05_N": "F30",
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"LA09_P": "B30",
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"LA09_N": "A30",
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"LA13_P": "A25",
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"LA13_N": "A26",
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"LA17_CC_P": "F20",
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"LA17_CC_N": "E20",
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"LA23_P": "B22",
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"LA23_N": "A22",
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"LA26_P": "B18",
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"LA26_N": "A18",
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"PG_M2C": "J29",
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"HA00_CC_P": "D12",
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"HA00_CC_N": "D13",
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"HA04_P": "F11",
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"HA04_N": "E11",
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"HA08_P": "E14",
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"HA08_N": "E15",
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"HA12_P": "C15",
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"HA12_N": "B15",
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"HA15_P": "H15",
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"HA15_N": "G15",
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"HA19_P": "H11",
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"HA19_N": "H12",
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"PRSNT_M2C_B": "M20",
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"CLK0_M2C_P": "D27",
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|
|
|
"CLK0_M2C_N": "C27",
|
|
|
|
|
"LA02_P": "H24",
|
|
|
|
|
"LA02_N": "H25",
|
|
|
|
|
"LA04_P": "G28",
|
|
|
|
|
"LA04_N": "F28",
|
|
|
|
|
"LA07_P": "E28",
|
|
|
|
|
"LA07_N": "D28",
|
|
|
|
|
"LA11_P": "G27",
|
|
|
|
|
"LA11_N": "F27",
|
|
|
|
|
"LA15_P": "C24",
|
|
|
|
|
"LA15_N": "B24",
|
|
|
|
|
"LA19_P": "G18",
|
|
|
|
|
"LA19_N": "F18",
|
|
|
|
|
"LA21_P": "A20",
|
|
|
|
|
"LA21_N": "A21",
|
|
|
|
|
"LA24_P": "A16",
|
|
|
|
|
"LA24_N": "A17",
|
|
|
|
|
"LA28_P": "D16",
|
|
|
|
|
"LA28_N": "C16",
|
|
|
|
|
"LA30_P": "D22",
|
|
|
|
|
"LA30_N": "C22",
|
|
|
|
|
"LA32_P": "D21",
|
|
|
|
|
"LA32_N": "C21",
|
|
|
|
|
"HA02_P": "D11",
|
|
|
|
|
"HA02_N": "C11",
|
|
|
|
|
"HA06_P": "D14",
|
|
|
|
|
"HA06_N": "C14",
|
|
|
|
|
"HA10_P": "A11",
|
|
|
|
|
"HA10_N": "A12",
|
|
|
|
|
"HA17_CC_P": "G13",
|
|
|
|
|
"HA17_CC_N": "F13",
|
|
|
|
|
"HA21_P": "J11",
|
|
|
|
|
"HA21_N": "J12",
|
|
|
|
|
"HA23_P": "L12",
|
|
|
|
|
"HA23_N": "L13",
|
|
|
|
|
}
|
|
|
|
|
),
|
|
|
|
|
("LPC",
|
|
|
|
|
{
|
|
|
|
|
"GBTCLK0_M2C_P": "N8",
|
|
|
|
|
"GBTCLK0_M2C_N": "N7",
|
|
|
|
|
"LA01_CC_P": "AE23",
|
|
|
|
|
"LA01_CC_N": "AF23",
|
|
|
|
|
"LA05_P": "AG22",
|
|
|
|
|
"LA05_N": "AH22",
|
|
|
|
|
"LA09_P": "AK23",
|
|
|
|
|
"LA09_N": "AK24",
|
|
|
|
|
"LA13_P": "AB24",
|
|
|
|
|
"LA13_N": "AC25",
|
|
|
|
|
"LA17_CC_P": "AB27",
|
|
|
|
|
"LA17_CC_N": "AC27",
|
|
|
|
|
"LA23_P": "AH26",
|
|
|
|
|
"LA23_N": "AH27",
|
|
|
|
|
"LA26_P": "AK29",
|
|
|
|
|
"LA26_N": "AK30",
|
|
|
|
|
"CLK0_M2C_P": "AF22",
|
|
|
|
|
"CLK0_M2C_N": "AG23",
|
|
|
|
|
"LA02_P": "AF20",
|
|
|
|
|
"LA02_N": "AF21",
|
|
|
|
|
"LA04_P": "AH21",
|
|
|
|
|
"LA04_N": "AJ21",
|
|
|
|
|
"LA07_P": "AG25",
|
|
|
|
|
"LA07_N": "AH25",
|
|
|
|
|
"LA11_P": "AE25",
|
|
|
|
|
"LA11_N": "AF25",
|
|
|
|
|
"LA15_P": "AC24",
|
|
|
|
|
"LA15_N": "AD24",
|
|
|
|
|
"LA19_P": "AJ26",
|
|
|
|
|
"LA19_N": "AK26",
|
|
|
|
|
"LA21_P": "AG27",
|
|
|
|
|
"LA21_N": "AG28",
|
|
|
|
|
"LA24_P": "AG30",
|
|
|
|
|
"LA24_N": "AH30",
|
|
|
|
|
"LA28_P": "AE30",
|
|
|
|
|
"LA28_N": "AF30",
|
|
|
|
|
"LA30_P": "AB29",
|
|
|
|
|
"LA30_N": "AB30",
|
|
|
|
|
"LA32_P": "Y30",
|
|
|
|
|
"LA32_N": "AA30",
|
2015-02-25 05:27:09 -05:00
|
|
|
"LA06_P": "AK20",
|
|
|
|
|
"LA06_N": "AK21",
|
|
|
|
|
"LA10_P": "AJ24",
|
|
|
|
|
"LA10_N": "AK25",
|
|
|
|
|
"LA14_P": "AD21",
|
|
|
|
|
"LA14_N": "AE21",
|
|
|
|
|
"LA18_CC_P": "AD27",
|
|
|
|
|
"LA18_CC_N": "AD28",
|
|
|
|
|
"LA27_P": "AJ28",
|
|
|
|
|
"LA27_N": "AJ29",
|
|
|
|
|
"CLK1_M2C_P": "AG29",
|
|
|
|
|
"CLK1_M2C_N": "AH29",
|
2015-04-02 07:58:20 -04:00
|
|
|
"LA00_CC_P": "AD23",
|
|
|
|
|
"LA00_CC_N": "AE24",
|
2015-02-25 05:27:09 -05:00
|
|
|
"LA03_P": "AG20",
|
|
|
|
|
"LA03_N": "AH20",
|
|
|
|
|
"LA08_P": "AJ22",
|
|
|
|
|
"LA08_N": "AJ23",
|
|
|
|
|
"LA12_P": "AA20",
|
|
|
|
|
"LA12_N": "AB20",
|
|
|
|
|
"LA16_P": "AC22",
|
|
|
|
|
"LA16_N": "AD22",
|
|
|
|
|
"LA20_P": "AF26",
|
|
|
|
|
"LA20_N": "AF27",
|
|
|
|
|
"LA22_P": "AJ27",
|
|
|
|
|
"LA22_N": "AK28",
|
|
|
|
|
"LA25_P": "AC26",
|
|
|
|
|
"LA25_N": "AD26",
|
|
|
|
|
"LA29_P": "AE28",
|
|
|
|
|
"LA29_N": "AF28",
|
|
|
|
|
"LA31_P": "AD29",
|
|
|
|
|
"LA31_N": "AE29",
|
|
|
|
|
"LA33_P": "AC29",
|
|
|
|
|
"LA33_N": "AC30",
|
2015-02-18 10:32:43 -05:00
|
|
|
}
|
|
|
|
|
)
|
|
|
|
|
]
|
|
|
|
|
|
2015-03-13 18:17:45 -04:00
|
|
|
class Platform(XilinxPlatform):
|
|
|
|
|
identifier = 0x4B37
|
|
|
|
|
default_clk_name = "clk156"
|
|
|
|
|
default_clk_period = 6.4
|
2014-06-07 06:24:19 -04:00
|
|
|
|
2015-03-13 18:17:45 -04:00
|
|
|
def __init__(self, toolchain="vivado", programmer="xc3sprog"):
|
2015-03-13 19:10:08 -04:00
|
|
|
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors,
|
2015-03-13 18:17:45 -04:00
|
|
|
toolchain=toolchain)
|
2015-03-29 06:16:33 -04:00
|
|
|
if toolchain == "ise":
|
|
|
|
|
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
|
|
|
|
|
elif toolchain == "vivado":
|
|
|
|
|
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
|
|
|
|
|
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
|
2015-03-13 18:17:45 -04:00
|
|
|
self.programmer = programmer
|
2014-08-22 06:44:10 -04:00
|
|
|
|
2015-03-13 18:17:45 -04:00
|
|
|
def create_programmer(self):
|
|
|
|
|
if self.programmer == "xc3sprog":
|
|
|
|
|
return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit")
|
|
|
|
|
elif self.programmer == "vivado":
|
|
|
|
|
return VivadoProgrammer()
|
2015-03-29 06:15:39 -04:00
|
|
|
elif self.programmer == "impact":
|
|
|
|
|
return iMPACT()
|
2015-03-13 18:17:45 -04:00
|
|
|
else:
|
|
|
|
|
raise ValueError("{} programmer is not supported".format(programmer))
|
2014-06-07 06:24:19 -04:00
|
|
|
|
2015-03-13 18:17:45 -04:00
|
|
|
def do_finalize(self, fragment):
|
2015-03-13 19:10:08 -04:00
|
|
|
XilinxPlatform.do_finalize(self, fragment)
|
2015-03-13 18:17:45 -04:00
|
|
|
try:
|
|
|
|
|
self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
|
|
|
|
|
except ConstraintError:
|
|
|
|
|
pass
|
|
|
|
|
try:
|
|
|
|
|
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
|
|
|
|
|
except ConstraintError:
|
|
|
|
|
pass
|
|
|
|
|
if isinstance(self.toolchain, XilinxISEToolchain):
|
|
|
|
|
self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";")
|
|
|
|
|
else:
|
|
|
|
|
self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
|
