litex/milkymist/dvisampler/__init__.py

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from migen.fhdl.structure import *
from migen.fhdl.module import Module
from migen.bank.description import AutoCSR
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from milkymist.dvisampler.edid import EDID
from milkymist.dvisampler.clocking import Clocking
from milkymist.dvisampler.datacapture import DataCapture
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from milkymist.dvisampler.charsync import CharSync
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from milkymist.dvisampler.wer import WER
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from milkymist.dvisampler.decoding import Decoding
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from milkymist.dvisampler.chansync import ChanSync
from milkymist.dvisampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction
from milkymist.dvisampler.dma import DMA
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class DVISampler(Module, AutoCSR):
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def __init__(self, pads, asmiport, n_dma_slots=2):
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self.submodules.edid = EDID(pads)
self.submodules.clocking = Clocking(pads)
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for datan in range(3):
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name = "data" + str(datan)
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invert = False
try:
s = getattr(pads, name)
except AttributeError:
s = getattr(pads, name + "_n")
invert = True
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cap = DataCapture(8, invert)
setattr(self.submodules, name + "_cap", cap)
self.comb += [
cap.pad.eq(s),
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cap.serdesstrobe.eq(self.clocking.serdesstrobe)
]
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charsync = CharSync()
setattr(self.submodules, name + "_charsync", charsync)
self.comb += charsync.raw_data.eq(cap.d)
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wer = WER()
setattr(self.submodules, name + "_wer", wer)
self.comb += wer.data.eq(charsync.data)
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decoding = Decoding()
setattr(self.submodules, name + "_decod", decoding)
self.comb += [
decoding.valid_i.eq(charsync.synced),
decoding.input.eq(charsync.data)
]
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self.submodules.chansync = ChanSync()
self.comb += [
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self.chansync.valid_i.eq(self.data0_decod.valid_o & \
self.data1_decod.valid_o & self.data2_decod.valid_o),
self.chansync.data_in0.eq(self.data0_decod.output),
self.chansync.data_in1.eq(self.data1_decod.output),
self.chansync.data_in2.eq(self.data2_decod.output),
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]
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###
self.submodules.syncpol = SyncPolarity()
self.comb += [
self.syncpol.valid_i.eq(self.chansync.chan_synced),
self.syncpol.data_in0.eq(self.chansync.data_out0),
self.syncpol.data_in1.eq(self.chansync.data_out1),
self.syncpol.data_in2.eq(self.chansync.data_out2)
]
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self.submodules.resdetection = ResolutionDetection()
self.comb += [
self.resdetection.valid_i.eq(self.syncpol.valid_o),
self.resdetection.de.eq(self.syncpol.de),
self.resdetection.vsync.eq(self.syncpol.vsync)
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]
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self.submodules.frame = FrameExtraction()
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self.comb += [
self.frame.valid_i.eq(self.syncpol.valid_o),
self.frame.de.eq(self.syncpol.de),
self.frame.vsync.eq(self.syncpol.vsync),
self.frame.r.eq(self.syncpol.r),
self.frame.g.eq(self.syncpol.g),
self.frame.b.eq(self.syncpol.b)
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]
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self.submodules.dma = DMA(asmiport, n_dma_slots)
self.comb += self.frame.frame.connect(self.dma.frame)
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self.ev = self.dma.ev
autocsr_exclude = {"ev"}