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3686 Commits

Author SHA1 Message Date
Florent Kermarrec 0332f73a7b build/xilinx/vivado: revert toolchain_path 2018-02-28 23:45:26 +01:00
Florent Kermarrec 2ff50a8882 build: fix merge 2018-02-28 23:10:24 +01:00
Florent Kermarrec 64e4e1ce84 build: merge with migen.build 27beffe7 2018-02-28 16:49:12 +01:00
Florent Kermarrec 0edfd9b901 boards/kcu105: regroup sfp tx and rx 2018-02-28 14:11:58 +01:00
Florent Kermarrec c5be6e26be README: add section for newcomers 2018-02-23 14:37:10 +01:00
Florent Kermarrec f372e8c880 README: cleanup 2018-02-23 14:15:41 +01:00
Florent Kermarrec fb088b79dd README: update, migen is no longer forked 2018-02-23 14:08:13 +01:00
Florent Kermarrec 1925ba176f replace litex.gen imports with migen imports 2018-02-23 13:38:19 +01:00
Florent Kermarrec 43164b9a2c remove migen fork from litex 2018-02-23 13:37:26 +01:00
Florent Kermarrec 212e1a7076 bump to 0.2.dev 2018-02-23 13:36:32 +01:00
Florent Kermarrec 64aa4ae4c0 uniformize with litex cores and make things more clear about what LiteX vs Migen/MiSoC 2018-02-22 11:52:10 +01:00
enjoy-digital aaf097056a
Merge pull request #64 from q3k/q3k/axi4lite 
Preliminary AXI4Lite support: CSR bridge
 2018-02-21 09:47:29 +01:00
Sergiusz Bazanski 688f26cc32 Change AXI interface and tidy code 
Inspired by parts of https://github.com/peteut/migen-misc/
 2018-02-21 00:00:58 +00:00
Sergiusz Bazanski 512ed2b3d6 Preliminary AXI4Lite CSR bridge support 
This change introduces an AXI4Lite to CSR bridge. Hopefully it will
become extended in the future with full AXI support and more structures
(Wishbone bridge, interconnect, ...). For now this will do.

The bridge has been simulated (and includes an FHDL testbench) and
tested in hardware (on a Zynq 7020).
 2018-02-20 21:27:51 +00:00
enjoy-digital 55fc9d2d6b
Merge pull request #60 from q3k/for-upstream/top-level-module-selection 
Top module selection (for Verilator and Diamond)
 2018-02-19 12:27:25 +01:00
enjoy-digital 7b5bd4041a
Merge pull request #57 from rohitk-singh/master 
WIP - BIOS: Flashboot without main ram
 2018-02-10 21:37:38 +01:00
Florent Kermarrec c14502807e board/targets/nexys4ddr: use MT47H64M16 2018-02-06 19:17:54 +01:00
Florent Kermarrec 95ebba428c boards/platforms/nexys4ddr: add user_sw, user_btn, fix ddr3 2018-02-06 19:08:46 +01:00
Florent Kermarrec ee4fa597b4 boards: add nexys4ddr 2018-02-06 14:43:20 +01:00
enjoy-digital 2ecd1b0666
Merge pull request #61 from PaulSchulz/master 
platform/arty.py: Move Pmod definitions to 'connectors' section.
 2018-01-26 01:58:37 +01:00
enjoy-digital c83ae98be3
Merge pull request #63 from cr1901/arty_s7 
boards/platforms: Add Arty S7 Board.
 2018-01-26 01:57:50 +01:00
William D. Jones 4607e5323f boards/platforms: Add Arty S7 Board. 2018-01-25 18:36:32 -05:00
Paul Schulz 0ac35300c4 Merge branch 'master' of https://github.com/enjoy-digital/litex into upstream 2018-01-24 13:32:42 +10:30
Florent Kermarrec 4f2725809e software/common: revert PYTHON to python3 (since breaking things) 2018-01-23 10:39:13 +01:00
Florent Kermarrec 4e168221d8 bios: fix riscv processor print 2018-01-23 10:33:05 +01:00
Florent Kermarrec d448874879 sim: rename top module to dut and use --top-module parameter (needed for picorv32 simulation) 2018-01-23 10:28:16 +01:00
Paul Schulz 3ac28ed6f7 platform/arty.py: Move Pmod definitions to 'connectors' section. 2018-01-23 16:11:25 +10:30
Sergiusz Bazanski ef511e7edc Specify top-level module in Lattice Diemond build script. 
When building multi-source files the toolchain gets confused as to which
module is top-level. This ensures that the build_name of the design is
selected.
 2018-01-23 01:17:04 +00:00
Sergiusz Bazanski ef6c517dad Build top module as 'dut' in Verilator and set it as top-level. 
When building a design with PicoRV32 we end up with multiple top-level
modules and Verilator becomes confused as to which is the right one.
This change ensures the dut.v generated by the sim build process has
it's top-level name set to 'dut' and that verilator is invoked with this
name.
 2018-01-23 01:15:28 +00:00
enjoy-digital a385143779
Merge pull request #59 from q3k/for-upstream/multiple-synthesis-directives 
Allow for multiple synthesis directives in specials.
 2018-01-23 01:43:23 +01:00
Sergiusz Bazanski 21bd26dcdd Allow for multiple synthesis directives in specials. 
This is needed to specify timing constraints on some Lattice Diamond
library specials, like the EHXPLLL.

To keep backwards compatibility we allow the directive to still be a
single string. If it's not, we assume it's an iterable.
 2018-01-23 00:27:49 +00:00
Florent Kermarrec 67f8718b26 minor cleanup 2018-01-23 00:35:20 +01:00
enjoy-digital d07ddd11d9
Merge pull request #58 from q3k/for-upstream/picorv32-support 
Implement IRQ for PicoRV32 on LiteX
 2018-01-22 22:09:46 +01:00
Sergiusz Bazanski 6daf3eabc5 Implement IRQ software support for RISC-V. 
Well, at least PicoRV32-specific. Turns out there is no RISC-V
specification for simple microcontroller-like interrupts, so PicoRV32
implements its' own based on custom opcodes.

It's somewhat esoteric, and for example doesn't offer a global interrupt
enable/disable. For this we implement a thin wrapper in assembly and
then expose it via a few helpers in irq.h.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski 2108c97b9b Import PicoRV32-specific instruction macros. 
These come from the PicoRV32 repo and are released under the public
domain [1].

[1] - 70f3c33ac8/firmware/custom_ops.S
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski cf74c781f4 Write init files that respect CPU's endianness. 
This is required for PicoRV32 support. We also drive-by enable
explicit specification of run= in Builder.build() by callers.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski 7176492231 Set the MABI and MArch of the riscv target. 
Again, this should be tunable, and synchronized with the core settings.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski 7ea5a26734 Enable hardware multiplier and divider in PicoRV32 
This should become tunable later once we can configure whether we link
in the soft mul library or not.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski 75e230aae7 Replace __riscv__ macros with __riscv. 
The __riscv__ form is deprecated [1].

[1] - https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski 20ed23443b Export trap signal from PicoRV32. 
This is useful for handling crashes from hardware.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski b0be563012 Bump PicoRV32 version. 2018-01-22 18:50:26 +00:00
Ewen McNeill 75e7f9505a BIOS: Flashboot without main ram 
Modified flashboot() to skip copy to main ram if there is no main
ram, and instead execute in place out of SPI flash.  (For this to
work the linker .ld will also need to redirect references to be
inside the SPI flash mapping.)
 2018-01-20 15:05:47 +11:00
Florent Kermarrec 3a5f93db5d software/bios: add litex logo 2018-01-19 18:41:13 +01:00
enjoy-digital d6877300c2
Merge pull request #56 from cr1901/mimasv2 
Add mimasv2 platform (pulled from litex-buildenv).
 2018-01-19 17:59:47 +01:00
William D. Jones c553fe2bf3 Add mimasv2 platform (pulled from litex-buildenv). 2018-01-19 06:16:04 -05:00
Tim Ansell d6f2f63794
Merge pull request #53 from mithro/allow-forcing-colorama 
Support forcing colorama colors on.
 2018-01-18 16:33:02 +11:00
Tim 'mithro' Ansell ead88ed66d Support forcing colorama colors on. 
This is needed if you want colors but are using pipes and similar.
 2018-01-18 14:41:45 +11:00
Tim Ansell fcc22350fb
Merge pull request #52 from ewen-naos-nz/tftp-alt-port 
BIOS: Support alternate TFTP server port
 2018-01-18 13:40:28 +11:00
Ewen McNeill 5ce8ca8e9b BIOS: TFTP: try UDP/69 if specified port fails 2018-01-18 13:10:28 +11:00
Ewen McNeill cb31266500 BIOS: set TFTP_SERVER_PORT from enviroment 2018-01-18 13:09:34 +11:00