69 Commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	79124d822b	Identifier	2012-05-17 01:41:41 +02:00
Sebastien Bourdeauducq	bb798176fc	Common include files	2012-05-16 10:20:04 +02:00
Sebastien Bourdeauducq	b6aa40d845	bios: automatically enable hardware memory controller and test memory	2012-05-15 19:29:26 +02:00
Sebastien Bourdeauducq	7ecfd60368	bios: more DDR diagnostic functions	2012-05-14 20:07:57 +02:00
Sebastien Bourdeauducq	8d4a42887e	ddrphy: working on hardware, simulation a bit messed up	2012-02-24 15:44:51 +01:00
Sebastien Bourdeauducq	17b2588321	ddrphy: reads OK, write data coming out 1/2 cycle too late	2012-02-24 15:05:52 +01:00
Sebastien Bourdeauducq	a363eb4a36	ddrphy: partly working	2012-02-24 13:54:10 +01:00
Sebastien Bourdeauducq	92ac69bae3	dfii: new design	2012-02-23 21:21:07 +01:00
Sebastien Bourdeauducq	f35cd4a85b	Prepare for new DDR PHY	2012-02-19 18:43:42 +01:00
Sebastien Bourdeauducq	1e4e092a55	bios: fix function prototypes	2012-02-18 21:06:35 +01:00
Sebastien Bourdeauducq	026457a98c	Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately.	2012-02-18 18:12:14 +01:00
Sebastien Bourdeauducq	c38de34a21	bios: DDR initialization skeleton	2012-02-17 18:47:04 +01:00
Sebastien Bourdeauducq	e5927e265f	bios: add flash target using m1nor	2012-02-17 18:16:29 +01:00
Sebastien Bourdeauducq	73fce59631	software: shell from original BIOS	2012-02-07 15:02:44 +01:00
Sebastien Bourdeauducq	ef0667d959	software: UART RX demo	2012-02-07 14:12:33 +01:00
Sebastien Bourdeauducq	fb22edc06a	software: enable -Wmissing-prototypes	2012-02-07 13:02:06 +01:00
Sebastien Bourdeauducq	4aaf48afb0	software: interrupt driven UART working	2012-02-06 23:53:29 +01:00
Sebastien Bourdeauducq	5cde57cb65	software: use new UART	2012-02-06 17:53:41 +01:00
Sebastien Bourdeauducq	45529d5941	BIOS: hello world	2012-02-05 20:01:28 +01:00