Tim 'mithro' Ansell
8daf5e32c1
Adding support for programming with FPGALink
...
Steps for getting it set up.
* Get libfpgalink dependencies
sudo apt-get install \
build-essential libreadline-dev libusb-1.0-0-dev python-yaml
* Build libfpgalink
wget -qO- http://tiny.cc/msbil | tar zxf -
cd makestuff; ./scripts/msget.sh makestuff/common
cd libs; ../scripts/msget.sh libfpgalink
cd libfpgalink; make deps
* Convert libfpgalink to python3
wget -O - http://www.swaton.ukfsn.org/bin/2to3.tar.gz | tar zxf -
cd examples/python
cp fpgalink2.py fpgalink3.py
../../2to3/2to3 fpgalink3.py | patch fpgalink3.py
* Set your path's correctly.
export LD_LIBRARY_PATH=$(pwd)/libfpgalink/lin.x64/rel:$LD_LIBRARY_PATH
export PYTHON_PATH=$(pwd)/libfpgalink/examples/python:$PYTHON_PATH
2015-07-02 16:44:39 +02:00
Tim 'mithro' Ansell
055f7d51fc
mibuild/xilinx: Adding programming with the Digilent Adept tools
2015-07-02 16:03:44 +02:00
Florent Kermarrec
7afa3d61d9
mibuild/xilinx: Xilinx's FPGAs do not necessary share the same primitives: add xilinx_s7_special_overrides and specific XilinxDDROutputS7 implementation
...
Fix DDROutput implementation on spartan6 (tested with LiteETH's GMII phy)
2015-07-02 09:42:12 +02:00
Yann Sionneau
4509265c70
travis: use use-local for conda install
...
http://conda.pydata.org/docs/build_tutorials/pkgs.html
2015-06-30 00:42:56 +02:00
William D. Jones
445f0f5d40
Remove self.programmer references in Mercury, as mercury programmer is not implemented.
2015-06-28 18:06:50 +02:00
William D. Jones
3ea7ef81a9
Add Mercury dev board to mibuild ( http://www.micro-nova.com/mercury/ )
2015-06-28 16:30:41 +02:00
Sébastien Bourdeauducq
f03c2325d9
Merge pull request #21 from psmears/patch-1
...
Minor improvements to wording
2015-06-24 10:46:58 +00:00
Florent Kermarrec
d77a5fc5ac
fhdl/specials: add Keep SynthesisDirective
2015-06-23 16:14:42 +02:00
Florent Kermarrec
71627cf9f0
bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software as a constant)
2015-06-19 08:37:16 +02:00
Florent Kermarrec
7d8f4d1009
mibuild/xilinx/ise: fix source and set source to False by default on Windows (tools supposed to be in the PATH)
2015-06-19 00:52:39 +02:00
Florent Kermarrec
743a5f6ea9
mibuild/xilinx/ise: simplify default_ise_path
2015-06-19 00:40:05 +02:00
William D. Jones
6370acd968
Xilinx Platforms now use cmd.exe on Windows instead of bash to run scripts
...
(remove MSYS dependency)
2015-06-19 00:30:22 +02:00
psmears
d435f30fa3
Minor improvements to wording
2015-06-18 12:26:22 +01:00
Florent Kermarrec
f8b1152b98
wishbone: add Cache (from WB2LASMI)
2015-06-17 15:31:49 +02:00
Yann Sionneau
6e876c63ad
pipistrello: fix FPGA speed grade
2015-06-14 23:19:27 +02:00
Florent Kermarrec
33b536e505
migen/bus/wishbone: add UpConverter and Converter wrapper (also rewrite DownConverter)
2015-06-02 19:29:38 +02:00
Florent Kermarrec
79624ce849
migen/genlib/fsm: fix delayed_enter when delay is negative (can happen when delay is generated from others parameters)
2015-06-02 19:26:42 +02:00
Sebastien Bourdeauducq
fd16b66bdf
genlib/cdc: add BusSynchronizer
2015-06-02 17:40:42 +08:00
Sebastien Bourdeauducq
57102ec160
setup.py: valid version number (fixes issue #12 )
2015-05-28 15:43:31 +08:00
Florent Kermarrec
a5f495aeac
fhdl/verilog: add reserved keywords
2015-05-23 14:01:08 +02:00
Florent Kermarrec
9cabcf14e9
migen/genlib/record: add leave_out parameter to connect
...
Modules doing dataflow adaptation often need to connect most of the signals between endpoints except the one concerned by the adaptation.
This new parameter ease that by avoid manual connection of all signals.
2015-05-23 13:59:09 +02:00
Guy Hutchison
5390540d3c
example of instance usage
2015-05-20 01:14:42 +08:00
Florent Kermarrec
ada131dbe0
vpi: avoid some code duplication between windows and linux
2015-05-13 10:48:08 +02:00
Florent Kermarrec
f6624b34f0
migen/actorlib/spi: apply missing CSR renaming
2015-05-13 10:17:31 +02:00
Florent Kermarrec
76302d7aa6
vpi: cleanup (thanks sb)
2015-05-13 10:13:14 +02:00
Florent Kermarrec
98cf103c65
vpi: fix and simplify windows simulation (ends of msg were ignored)
2015-05-13 03:03:34 +02:00
Florent Kermarrec
b0f159421c
Merge branch 'master' of https://github.com/m-labs/migen
2015-05-12 16:16:24 +02:00
Florent Kermarrec
88a406ebec
migen/genlib/misc: replace Timeout with WaitTimer from artiq
2015-05-12 16:14:58 +02:00
Yann Sionneau
9194fe43a1
travis: install conda dependencies after activating the virtual env
2015-05-12 14:06:16 +02:00
Yann Sionneau
c1088f4666
travis: get-anaconda.sh does not take args anymore
2015-05-12 13:58:08 +02:00
William D. Jones
fe6eef7069
Windows simulation support
2015-05-09 21:09:52 +08:00
Robert Jordens
99fb0d4619
ise: move -user_new_parser to xst_opt
2015-05-08 11:18:45 +08:00
Florent Kermarrec
70bc4ecb59
mibuild/platforms/pipistrello: add _n suffix to usb fifo pins
2015-05-01 15:49:33 +02:00
Florent Kermarrec
aea7308051
mibuild/platforms/minispartan6: rename ftdi_fifo to usb_fifo and fix rd_n/wr_n swap
2015-05-01 15:48:42 +02:00
Sebastien Bourdeauducq
01e2343978
doc: remove cordic
2015-05-01 14:07:38 +08:00
Alain Péteut
96bff77c36
add examples tests
2015-05-01 00:50:17 +08:00
Florent Kermarrec
1cbc468bda
migen/actorlib/packet: add Packetizer and Depacketizer
2015-04-28 18:44:05 +02:00
Florent Kermarrec
0da9311d70
migen/genlib: avoid use of floating point in reverse_bytes
2015-04-27 21:04:18 +02:00
Florent Kermarrec
3ce5ff3722
migen/actorlib: add packet.py to manage dataflow packets (Arbiter, Dispatcher, Header definitions, Buffer)
2015-04-27 15:14:38 +02:00
Florent Kermarrec
f976b1916a
migen/actorlib/misc: add BufferizeEndpoints
...
BufferizeEndpoints provides an easy way improve timings of chained dataflow modules and avoid polluting code with internals buffers.
2015-04-27 15:12:01 +02:00
Florent Kermarrec
e96ba1e46f
migen/genlib/misc: add reverse_bytes
2015-04-27 15:08:10 +02:00
William D. Jones
472665b81d
Add a command line option (-use_new_parser yes) to Xilinx XST to force use of the newer parser for older FPGAs.
2015-04-25 23:01:07 +08:00
Florent Kermarrec
73a1687562
migen/test: for now desactivate test_generic_syntax (travis-ci's Verilator needs to be upgraded?)
2015-04-24 13:24:52 +02:00
Florent Kermarrec
67702f25ab
migen/fhdl/verilog: _printheader/_printcomb, remove default value of arguments which are not used in internal functions. (thanks sb)
2015-04-24 12:54:08 +02:00
Florent Kermarrec
bc30fc57e7
migen/fhdl: give explicit names to syntax specialization when asic_syntax is used
2015-04-24 12:14:14 +02:00
Florent Kermarrec
61c3efc5f5
migen/test: rename asic_syntax to test_syntax and simplify
2015-04-24 12:00:46 +02:00
Yann Sionneau
b93df693a4
travis: add conda package generation and upload + build doc
2015-04-23 14:15:31 +08:00
Yann Sionneau
7280bdb9d4
Add conda recipe for Migen
2015-04-23 14:15:15 +08:00
Yann Sionneau
2f45d4640b
doc: fix warnings during doc build
2015-04-23 12:34:17 +08:00
Guy Hutchison
e5b170f02d
travis: install verilator
2015-04-22 12:30:03 +08:00