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1308 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 0b9c6720d8 doc: Constant 2015-09-17 11:05:57 +08:00
Sebastien Bourdeauducq f5ab734bdf fhdl/verilog: fix case value sort 2015-09-17 08:03:48 +08:00
Sebastien Bourdeauducq e940c6d9b9 fhdl/structure: introduce Constant, autowrap for eq/ops, fix Signal as dictionary key problem 2015-09-15 12:38:02 +08:00
Sebastien Bourdeauducq 42afba2bbc fhdl/decorators: remove traces of deprecated API 2015-09-12 19:44:35 +08:00
Sebastien Bourdeauducq eb921fb957 genlib: remove reverse_bytes, FlipFlop, Counter 2015-09-12 19:40:29 +08:00
Sebastien Bourdeauducq 9667d61e84 genlib: cleanup CRG 2015-09-12 19:40:07 +08:00
Sebastien Bourdeauducq 1bdb9bee22 fhdl/decorators: remove deprecated API 2015-09-12 19:34:44 +08:00
Sebastien Bourdeauducq 336728413a simplify imports, migen.fhdl.std -> migen 2015-09-12 19:34:07 +08:00
Sebastien Bourdeauducq b43495aab1 build/xilinx: minor cleanup 2015-09-12 16:48:25 +08:00
Sebastien Bourdeauducq 047d1f48b5 test/support,signed,sort: use new simulator 2015-09-12 16:28:21 +08:00
Sebastien Bourdeauducq 8ee361ffe2 sim: refactor comb commit 2015-09-12 16:27:59 +08:00
Sebastien Bourdeauducq 5fa7f7414f sim: support eval of nested lists 2015-09-12 16:01:53 +08:00
Sebastien Bourdeauducq 9556c335ea genlib/sort: remove unneeded import 2015-09-12 15:21:42 +08:00
Sebastien Bourdeauducq 308c5d7a78 examples/graycounter: use new simulator 2015-09-12 15:14:21 +08:00
Sebastien Bourdeauducq fa6d96bb9a test/examples: do not attempt to run deleted examples 2015-09-12 15:13:45 +08:00
Sebastien Bourdeauducq 7bd72a16df sim: support clock domains without sync 2015-09-12 15:12:57 +08:00
Sebastien Bourdeauducq fd986210f8 simulator: support generators 2015-09-10 21:44:14 -07:00
Sebastien Bourdeauducq 10d89d81f4 new simulator: basic execution 2015-09-10 20:33:45 -07:00
Sebastien Bourdeauducq 49ef182305 fhdl/tools: add input lister 2015-09-10 20:33:10 -07:00
Sebastien Bourdeauducq f9849fb8be style 2015-09-10 20:32:47 -07:00
Sebastien Bourdeauducq 714ae43ab8 fhdl: remove features new simulator won't use 2015-09-10 18:29:57 -07:00
Sebastien Bourdeauducq 91ab3f0d01 remove genlib.misc.optree (use reduce instead) 2015-09-10 13:56:56 -07:00
Yves Delley 1dcd2ac1c0 fixed bug in value_bits_sign of mul operatiors 2015-09-10 10:53:26 -07:00
Sebastien Bourdeauducq 86f34e82c3 mibuild -> migen.build 2015-09-10 10:53:15 -07:00
Sebastien Bourdeauducq f1dc008d32 Simulator will be rewritten 2015-09-05 15:07:00 -06:00
Sebastien Bourdeauducq dec2e23fc7 Remove code that will be into MiSoC or other packages. 2015-09-05 15:06:04 -06:00
Florent Kermarrec 5253b0c06e migen/actorlib/packet: fix source.error in Depacketizer 2015-08-19 01:12:07 +02:00
Florent Kermarrec 9210df9e9f mibuild/xilinx/ise: update synthesis with yosis 2015-08-19 01:12:05 +02:00
Florent Kermarrec 646667213e migen/flow/actor: fix sop/eop validation in PipelinedActor (stb can be inactive when pipe_ce is active) 2015-08-09 19:54:38 +02:00
Ryan Verner 9c902bcd86 Port fpgalink_programmer to use newer fl library. 
* See change in 2074e51a33
 2015-08-04 21:42:29 +08:00
Sebastien Bourdeauducq df2306ab88 try to use the new anaconda-client 2015-07-31 13:46:28 +08:00
Sebastien Bourdeauducq abbb76ce84 ise: do not use LCK_cycle:6 by default 2015-07-29 11:09:42 +08:00
Robert Jordens a11d065546 pipistrello: fix cts/rts 
* use the same perspective as for tx/rx (flipped w.r.t. the ftdi chip)
* add pullups in case target or host attempt to use handshaking
 2015-07-27 21:46:24 -06:00
Sebastien Bourdeauducq b7784fcbd7 platforms/kc705: add GPIO SMA 2015-07-28 00:19:39 +08:00
Sebastien Bourdeauducq f32f9be17a resetless -> reset_less 2015-07-27 11:46:11 +08:00
Sebastien Bourdeauducq cc6877df9e fhdl: allow use of ResetSignal() on resetless clock domains 2015-07-27 01:51:52 +08:00
Sebastien Bourdeauducq 5a535ef347 Revert "migen/actorlib/fifo: add FIFO wrapper function" 
This reverts commit d0a19c4be8.
 2015-07-24 19:25:36 +08:00
Florent Kermarrec d0a19c4be8 migen/actorlib/fifo: add FIFO wrapper function 
Allow automatic instantiation of the correct fifo (SyncFIFO or AsyncFIFO) according to the clock domains passed in argument.
 2015-07-24 13:02:54 +02:00
Florent Kermarrec 1f1ff5a5e9 migen/fhdl/tools: fix rename_clock_domain when new == old 
Clock domain renaming should support new == old to allow programmatically determined clock domain renaming.
 2015-07-24 12:48:51 +02:00
Florent Kermarrec 493f424ebd Merge branch 'master' of https://github.com/m-labs/migen 2015-07-22 21:46:23 +02:00
Florent Kermarrec 5713ae381a actorlib/packet/Depacketizer: manage layouts without error signal 2015-07-22 21:43:21 +02:00
numato 09b33346be Removed drive strength constraints on VGA/Audio signals 2015-07-14 23:00:26 +02:00
Robert Jordens 6468fa3db4 xilinx: ensure we chdir() back after build 2015-07-14 12:53:43 -06:00
Sebastien Bourdeauducq 52bdc29528 mimasv2: style, consistency with other boards 2015-07-14 19:56:00 +02:00
numato e56d80c7a0 Adding support for Numato Lab Mimas V2 platform 2015-07-14 19:42:51 +02:00
Sebastien Bourdeauducq ea8ffd8e80 platforms/kc705: style 2015-07-14 19:42:44 +02:00
Robert Jordens 8d6aa82082 mibuild/openocd.py: add support 
Tested with pipistrello and kc705. Needs patches from
https://github.com/jordens/openocd/tree/bscan_spi waiting
to be merged in the openocd queue.
 2015-07-07 21:01:31 -06:00
Sebastien Bourdeauducq 73ea404380 Merge branch 'master' of https://github.com/m-labs/migen 2015-07-05 10:53:32 +02:00
Tim 'mithro' Ansell 1d1f8510d3 Allow using non-milkymist cables with UrJTAG. 2015-07-05 10:53:09 +02:00
Tim 'mithro' Ansell 0df9c16e69 mibuild: Adding error checking around xsvf generation 2015-07-02 16:51:03 +02:00