11e8491547
platforms/arty_s7: keep up to date with Migen
2018-07-05 12:02:14 +02:00
d35dc5cdea
platforms/arty: merge with Migen
2018-07-05 11:18:49 +02:00
fa0215660b
platforms/kc705: keep up to date with Migen
2018-07-05 10:43:26 +02:00
b9f3b49c63
platforms/de0nano: keep up to date with Migen
2018-07-05 10:42:45 +02:00
df99cc66e8
bios/sdram: also check for last read of scan to choose optimal window
2018-07-02 14:12:27 +02:00
8ce7fcb237
bios/main: add cpu frequency to banner
2018-07-02 13:47:18 +02:00
477d224921
bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal.
2018-07-02 13:46:48 +02:00
9e737d3c57
soc/cores/code_8b10b: update (from misoc)
2018-06-29 14:24:44 +02:00
d58eb4ecb7
bios/sdram: use new phy, improve scan, allow disabling high skew
2018-06-28 18:43:48 +02:00
692cb14245
software/bios: fix picorv32 boot_helper
2018-06-28 11:42:43 +02:00
b5ee110e63
bios/sdram: add write/read leveling scans
2018-06-27 15:31:54 +02:00
34b2bd0c28
boards: add genesys2 (platform with clk/serial/dram/ethernet + target)
2018-06-27 11:27:05 +02:00
8edc659d7d
soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases)
2018-06-19 11:15:29 +02:00
2c13b701f5
soc/integration/cpu_interface: add shadow_base parameter
2018-06-18 18:01:47 +02:00
7444992999
soc: bios: fix windows build
...
The BIOS builds just fine on Windows, but afterwards tries to run
`chmod`. This command does not exist on Windows, and is unnecessary.
Add a conditional guard to prevent this command from running on Windows.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-06-18 17:13:54 +08:00
18f86881d9
targets: change a7/k7ddrphy imports to s7ddrphy
2018-06-12 15:40:45 +02:00
3e723d152a
soc/cores/cpu: add add_sources static method
...
When creating SoC with multiple sub-SoC already generated, we need an
easy way to add cpu sources.
2018-06-12 10:54:20 +02:00
7353197e21
fix the vexriscv boot helper
2018-05-31 01:24:22 +08:00
34a9303448
Fix for missing connectors for arty boards
2018-05-24 21:55:52 +03:00
e7d1683e34
litex_term: cleanup getkey and revert default settings on KeyboardInterrupt
2018-05-24 08:10:05 +02:00
6854c7f5fc
soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/ )
2018-05-09 15:39:25 +02:00
66229c8c05
add VexRiscv support (imported/adapted from misoc)
2018-05-09 15:03:37 +02:00
f60da4a5dc
add VexRiscv submodule
2018-05-09 14:39:31 +02:00
d149f386c9
allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32)
2018-05-09 13:26:55 +02:00
c3652935d9
build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)
2018-05-01 12:02:54 +02:00
121eaba722
soc/intergration/soc_core: don't delete uart/timer0 interrupts
2018-05-01 00:46:26 +02:00
39ffa532b0
xilinx/programmer: fix programmer
2018-05-01 00:44:13 +02:00
c001b8eaf6
build/xilinx/vivado: add vivado ip support
2018-04-12 17:55:46 +02:00
43f8c230a7
soc_core: uncomment uart interrupt deletion
2018-04-12 17:23:46 +02:00
d7c7474670
gen/sim: fix import to use litex simulator instead of migen simulator
2018-04-04 15:40:53 +02:00
b7f7c8d159
build/xilinx/common/XilinxDDROutputImplS6: DDR_ALIGNMENT="C0" requires SRTYPE to be "ASYNC"
2018-03-12 09:33:05 +01:00
4324c6f666
bios/sdram: update kuddrphy initialization procedure
2018-03-08 13:54:30 +01:00
90dcd45f0b
soc/software/main: go to new line at startup
2018-03-07 21:39:10 +01:00
6706b24167
software/bios/main: add missing space
2018-03-07 15:24:39 +01:00
2a50a8021a
soc/integration/soc_core: improve error message for missing csrs
2018-03-05 09:59:06 +01:00
5ef34500f7
Improving error message when csr name is not found.
...
Before;
```
"/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/integration/soc_core.py",
line 258, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'core'
```
Now;
```
Traceback (most recent call last):
File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 259, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'ddrphy'
The above exception was the direct cause of the following exception:
Traceback (most recent call last):
...
File "XXXX/github/enjoy-digital/litex/litex/soc/interconnect/csr_bus.py", line 199, in scan
mapaddr = self.address_map(name, None)
File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 269, in get_csr_dev_address
) from e
RuntimeError: Unable to find ddrphy in your SoC's csr address map.
Check BaseSoC.csr_map in XXXX/github/enjoy-digital/litex/litex/boards/targets/arty.py
Found l2_cache, timer0, ddrphy2, buttons, sdram, identifier_mem, uart, uart_phy, leds, crg in the csr_map
```
2018-03-03 16:02:44 -08:00
ab2a3277c3
Merge pull request #67 from cr1901/vivado-paths
...
xilinx/vivado: Provide a fallback mechanism for using the same root f…
2018-03-03 08:29:18 +01:00
db20df49f4
Merge pull request #65 from cr1901/tinyfpga-serial
...
platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it
2018-03-03 08:28:57 +01:00
2b00b7eba4
xilinx/vivado: Provide a fallback mechanism for using the same root for Vivado and ISE toolchains.
2018-03-02 21:48:49 -05:00
fa6b256198
build/xilinx/platform: fix merge
2018-03-03 00:07:50 +01:00
d40c57739c
boards/arty_s7: Fix IOStandard on System Clock.
2018-03-02 13:35:43 -05:00
0332f73a7b
build/xilinx/vivado: revert toolchain_path
2018-02-28 23:45:26 +01:00
2ff50a8882
build: fix merge
2018-02-28 23:10:24 +01:00
64e4e1ce84
build: merge with migen.build 27beffe7
2018-02-28 16:49:12 +01:00
0edfd9b901
boards/kcu105: regroup sfp tx and rx
2018-02-28 14:11:58 +01:00
e71593d67e
platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it
...
optional via `add_extension`.
2018-02-27 18:41:35 -05:00
1925ba176f
replace litex.gen imports with migen imports
2018-02-23 13:38:19 +01:00
43164b9a2c
remove migen fork from litex
2018-02-23 13:37:26 +01:00
688f26cc32
Change AXI interface and tidy code
...
Inspired by parts of https://github.com/peteut/migen-misc/
2018-02-21 00:00:58 +00:00
512ed2b3d6
Preliminary AXI4Lite CSR bridge support
...
This change introduces an AXI4Lite to CSR bridge. Hopefully it will
become extended in the future with full AXI support and more structures
(Wishbone bridge, interconnect, ...). For now this will do.
The bridge has been simulated (and includes an FHDL testbench) and
tested in hardware (on a Zynq 7020).
2018-02-20 21:27:51 +00:00
Florent Kermarrec
Sean Cross
bunnie
Deano Calver
Dolu1990
Tim 'mithro' Ansell
William D. Jones
Sergiusz Bazanski