4c426b36f3
fifo: add support for depth=2
2014-06-15 23:58:46 +02:00
70a2ee4368
migen/bank/description: add reset parameter to CSRStatus
2014-06-15 23:54:38 +02:00
26717a49fe
kc705: use string default arg
2014-06-07 13:41:46 +02:00
be0d86f57f
initial Vivado support
2014-06-07 12:24:28 +02:00
518a6822d9
mibuild/platforms: use add_period_constraint
2014-05-21 21:02:06 +02:00
a1a57fd962
mibuild: expose add_period_constraint (easier to use for simple designs than vendor specific code)
2014-05-21 21:02:06 +02:00
6c78e6f729
mibuild/altera_quartus: use default gui command line parameters (enable pll constraints propagation) and remove deprecated methods
2014-05-21 21:02:06 +02:00
e9db646134
mibuild: remove useless 'reduce_control_sets auto'
2014-05-12 19:11:11 +02:00
9c1d95f6a4
wishbone2lasmi: fix wordbits computation
2014-05-01 13:32:18 +02:00
65e8b2742a
de0nano: call sdram mask dm, not dqm (follow other platforms and gensdrphy)
2014-04-25 10:40:26 +02:00
29ed3918cc
fhdl: forbid zero-length signals
2014-04-18 15:01:50 +02:00
86f852a5f1
wishbone2lasmi: support lasmim data_width < wishbone data_width
2014-04-18 15:00:53 +02:00
8c03cb0491
mibuild: force shell script generation to unix format (will be executed with cygwin's bash on windows)
2014-04-17 19:43:56 +02:00
d1a96bc49f
mibuild/altera_quartus: enforce use of SystemVerilog in Quartus (Verilog does not support global parameters)
2014-04-17 19:43:24 +02:00
a36a208dd1
sim: use (mandatory) ncycles when starting a simulation with no active functions
2014-04-13 15:16:27 +02:00
fef08e8c70
mibuild: add bitstream_ext parameter to platforms
2014-04-11 23:28:39 +02:00
82e4980f5c
mibuild/altera_quartus: set top_level_entity
2014-04-11 23:27:04 +02:00
600ce55f91
mibuild/altera_quartus: add support for verilog include
2014-04-11 23:24:51 +02:00
ce378f47d3
test/SyncFIFOCase: better test bench termination
2014-04-07 00:05:08 +02:00
e94f30f15d
mibuild/xilinx_ise: move overwrite option to default options
2014-04-05 12:15:15 +02:00
9ff6cc8403
mibuild/xilinx: make par and map options configurable
2014-04-05 12:15:14 +02:00
ac1363565d
genlib/fifo: add SyncFIFOClassic and SyncFIFOBuffered
2014-04-05 12:15:14 +02:00
9deddbdfbc
test/test_cordic: fix for new Simulation API
2014-03-24 15:01:44 -07:00
7649028bdc
test/support: fix default ncycles
2014-03-24 15:01:44 -07:00
0023b742e4
genlib/coding: gracefully handle flen(i) < 2
2014-03-19 18:12:27 -07:00
0836f2814a
bus/csr: new simulation api
2014-03-19 18:12:27 -07:00
b03d9f4c14
genlib/fifo: add flush, expose level in SyncFIFO
...
AsyncFIFO would need versions of flush and level in each clock domain
plus some handshaking on double flush.
Signed-off-by: Robert Jordens <jordens@gmail.com>
2014-03-15 23:10:46 -07:00
bf6ab2b4f6
mibuild/generic_platform: fix default value for connectors
2014-02-17 17:40:15 +01:00
c98b9ecbcb
mibuild/platforms/papilio_pro: add expansion connectors
2014-02-16 23:54:11 +01:00
cb2c9f9f7a
mibuild: support for expansion connectors
2014-02-16 23:53:50 +01:00
d26330a9b9
Update doc with new simulation API
2014-02-07 23:08:59 +01:00
2ab939e69d
fix SimActor TB terminations
2014-01-28 00:03:56 +01:00
90f0dfad63
Add 'passive' simulation functions that are not taken into account while determining when to stop the simulator
2014-01-27 23:58:46 +01:00
63c1d7e4b7
New simulation API
2014-01-26 22:19:43 +01:00
8f69d9b669
bank/eventmanager: add SharedIRQ
2014-01-06 22:13:06 +01:00
be1c8551d2
migen/fhdl/tools: speed up group_by_targets (halves the mixxeo runtime)
2013-12-17 18:40:49 +01:00
4e9dc297fd
platforms/rhino: add GPMC wait pin
2013-12-14 14:32:34 +01:00
a20688f777
fhdl/simplify/FullMemoryWE: fix WE slice for multi-port mems
2013-12-13 00:02:50 +01:00
3196462311
add support for Verilog include paths
2013-12-12 23:17:51 +01:00
adda930c68
fhdl/simplify: add FullMemoryWE decorator that splits memories to remove partial WEs
2013-12-12 17:37:31 +01:00
adffec35f6
utils/misc: add gcd_multiple function to compute GCD or any number of integers
2013-12-12 17:36:50 +01:00
c13fe1bc63
specials/Memory: allow for more flexibility in memory port signals
2013-12-12 17:36:17 +01:00
135a4fea25
fhdl/verilog: fix representation of negative integers
...
Give the explicit two's complement representation for the given bit width.
This results in less readable code compared to using unary minus,
but fixes a bug when trying to represent the most negative integer.
2013-12-11 22:26:10 +01:00
d6cb981c7a
migen/test/test_signed: add a (currently failing) signed comparison testcase
2013-12-10 23:33:53 +01:00
487df5b174
migen/fhdl/bitcontainer: fix signed arrays (map is an iterator)
2013-12-10 23:32:12 +01:00
fe0263bb9a
mibuild/xilinx_ise: use ngdbuild_opt also for xst case
2013-12-06 12:15:22 +01:00
0aa6329edb
mibuild/xilinx_ise: add support for custom tools and options
2013-12-06 09:16:07 +01:00
e09e85ec8e
usrp_b100 platform
2013-12-03 22:51:52 +01:00
5447eb51ba
add zedboard platform
2013-12-03 22:51:52 +01:00
bfdc14fbc3
add initial ztex_115d platform
2013-12-03 22:51:52 +01:00
Florent Kermarrec
Sebastien Bourdeauducq
Robert Jordens
Sebastien Bourdeauducq