Commit Graph

78 Commits

Author SHA1 Message Date
Florent Kermarrec c0c17030fd spi_flash: simplify usage by removing cmd, cmd_width, addr_width parameters 2014-09-04 15:23:39 +08:00
Sebastien Bourdeauducq 36434b62f0 sdram: merge DFII_PIX_RDDATA_SIZE and DFII_PIX_WRDATA_SIZE 2014-09-03 15:02:38 +08:00
Sebastien Bourdeauducq a7b4550e59 sdramphy/initsequence: cleanup and expose DDR3 MR1 value 2014-09-03 14:21:30 +08:00
Florent Kermarrec 114890ee80 sdramphy/initsequence: clean up mr1/mr2 computation on DDR3 and enable Dynamic ODT 2014-09-02 10:54:29 +08:00
Sebastien Bourdeauducq 2234f50223 k7ddrphy: add bitslip control for incoming DQ 2014-09-01 19:54:39 +08:00
Sebastien Bourdeauducq 5483b37c8f k7ddrphy: write leveling and read calibration support 2014-08-31 21:54:28 +08:00
Sebastien Bourdeauducq 19abe2b888 k7ddrphy: do not register T at SERDES (fixes timing problem) 2014-08-31 21:53:35 +08:00
Sebastien Bourdeauducq 541e5abbc7 k7ddrphy: update comment 2014-08-22 19:02:57 +08:00
Sebastien Bourdeauducq 66fe45ba96 k7ddrphy: decrease CAS latency to account for cmd/data flight time 2014-08-22 18:46:01 +08:00
Sebastien Bourdeauducq b94647ab16 k7ddrphy: suppress idiotic bitgen warning about ISERDES IOBDELAY parameter 2014-08-22 18:45:25 +08:00
Florent Kermarrec 1c381acc6f k7ddrphy: fix read_latency (CL is 2 sys_clk since we use quarter rate) 2014-08-14 22:46:06 +08:00
Florent Kermarrec acbba37f5f k7ddrphy: set bitslip to 0 on ISERDESE2 (needed at least for sim) 2014-08-14 22:46:06 +08:00
Florent Kermarrec 2e4bfe154f k7ddrphy: add ODELAYE2 on dm path to match dq path (ODELAYE2 even configure with a delay of 0 generates a delay) 2014-08-14 22:46:06 +08:00
Florent Kermarrec bb85f29f91 k7ddrphy: fix write_latency and take care of OSERDESE2 latency on oe 2014-08-14 22:46:06 +08:00
Florent Kermarrec 85b29c883a sdramphy/initsequence: fix and add format_mr0 function 2014-08-14 14:17:54 +08:00
Florent Kermarrec 9844c25df9 k7ddrphy: add SERDES reset 2014-08-14 14:16:41 +08:00
Florent Kermarrec 194a5a0491 lasmicon: fix reset_n level 2014-08-14 14:15:48 +08:00
Sebastien Bourdeauducq c8dd4d2b40 k7ddrphy: send rddata_valid on all phases 2014-08-09 11:00:13 +08:00
Sebastien Bourdeauducq 8deadc5760 dfii: drive ODT and RESET_N 2014-08-08 21:56:35 +08:00
Sebastien Bourdeauducq 1322c0484b lasmicon: drive ODT and RESET_N 2014-08-08 21:55:34 +08:00
Sebastien Bourdeauducq 0550cbb3ce lasmicon: add CWL to PHY settings 2014-08-08 21:55:12 +08:00
Sebastien Bourdeauducq 777ebb7875 sdramphy/gensdrphy: fix rddata_en generation 2014-08-08 21:41:07 +08:00
Sebastien Bourdeauducq a2c7ff4c0c sdramphy: initial K7 DDR3 support 2014-08-08 21:28:26 +08:00
Florent Kermarrec 293ac09673 sdramphy/bios: make sdrrd/sdrwr generic 2014-08-08 19:25:10 +08:00
Sebastien Bourdeauducq cfc37a3fa5 sdramphy/initsequence: rewrite DDR3 initialization sequence 2014-08-08 19:15:05 +08:00
Sebastien Bourdeauducq e8db842538 s6ddrphy: fix DFI interface data width computation 2014-08-08 19:14:15 +08:00
Sebastien Bourdeauducq efb2466c7e gensoc: add id for KC705 2014-08-06 23:53:51 +08:00
Florent Kermarrec d1ff43faa7 gensoc/cpuif: do not generate access functions for registers > 64 bits 2014-08-04 22:38:19 +08:00
Sebastien Bourdeauducq 213cb43ae5 Keep only basic SoC designs in MiSoC 2014-08-03 12:30:15 +08:00
Florent Kermarrec 25b3aff6f1 sdramphy: add init sequence for DDR3 2014-07-31 10:29:32 +08:00
Yann Sionneau 32171da46d Better UART baudrate generator, and testbench
This enables high speed (tested to 4Mbps) operation.
2014-07-31 10:24:52 +08:00
Florent Kermarrec d4833cb3dc cpuif: remove limitations on csr data_width 2014-06-28 17:39:55 +02:00
Robert Jordens 81ed92d3b9 spiflash: redundant slice 2014-05-24 10:39:07 +02:00
Florent Kermarrec f4c0648289 gensdrphy: fix dm generation 2014-05-21 21:16:06 +02:00
Florent Kermarrec 54339a6d5b gensdrphy: fix memtype and change phase shift in comments. 2014-05-16 16:52:24 +02:00
Sebastien Bourdeauducq 6298624f98 sdramphy: remove fixed parameters 2014-05-14 16:08:40 +02:00
Sebastien Bourdeauducq 1c08aeb21c Initial mor1kx (OpenRISC) support
Based on milkymist-ng-mor1kx by Stefan Kristiansson
2014-05-14 10:24:56 +02:00
Florent Kermarrec 774464155a gensdrphy: clean up and implement data mask 2014-05-01 16:17:50 +02:00
Robert Jordens 3ab9f234d0 gensdrphy: use 'dm' not 'dqm' (follow s6ddrphy and majority of platforms) 2014-04-25 10:38:57 +02:00
Florent Kermarrec 1adceb8276 sdramphy: move and clean up s6ddrphy, add generic SDRAM PHY 2014-04-17 19:38:25 +02:00
Sebastien Bourdeauducq 9e784fc82c Generate mem.h from SoC description 2014-02-21 17:55:05 +01:00
Sebastien Bourdeauducq bdb47e7977 dvisampler: replace parity with sof 2014-02-13 22:45:27 +01:00
Sebastien Bourdeauducq 42c25f44ad videostream: add downscaler core + test 2014-02-10 00:12:57 +01:00
Sebastien Bourdeauducq 2a3803d3a1 videostream: add single chopper 2014-02-09 00:53:30 +01:00
Sebastien Bourdeauducq b6a00e86e4 videostream: add compacter and packer 2014-02-08 18:39:01 +01:00
Sebastien Bourdeauducq 25acf17312 Refresh testbenches and convert to new API 2014-01-28 13:50:01 +01:00
Sebastien Bourdeauducq e464935119 downscaler: add chopper module 2014-01-21 15:56:51 +01:00
Sebastien Bourdeauducq ad974a07ef gensoc: support for user-defined UART and add default values for SRAM and L2 sizes 2014-01-06 22:12:42 +01:00
Sebastien Bourdeauducq c95b9d6d76 gensoc: use add_verilog_include_path 2013-12-12 23:17:16 +01:00
Sebastien Bourdeauducq 55a39269d2 gpio: add InOut 2013-12-06 00:06:53 +01:00