Commit Graph

13 Commits

Author SHA1 Message Date
Florent Kermarrec a99aa9c7fd uart: rename wishbone to bridge 2015-05-09 16:24:28 +02:00
Florent Kermarrec fb5397aa82 uart: remove litescope dependency for UARTWishboneBridge and remove frontend 2015-05-09 16:08:20 +02:00
Florent Kermarrec c98bd9fd79 rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq) 2015-05-02 17:07:58 +02:00
Florent Kermarrec 3ebe877fd2 use similar names for wishbone bridges and move wishbone drivers to [core]/software 2015-05-02 16:22:30 +02:00
Florent Kermarrec c03c41eb77 litescope: rename host directory to software (to be coherent with others cores) 2015-05-01 20:45:02 +02:00
Florent Kermarrec 1281a463d6 litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
Florent Kermarrec dc8d844579 liteusb: begin refactoring and simplification (wip) 2015-04-27 15:22:49 +02:00
Florent Kermarrec 20dd6d3047 litepcie: use new Migen modules from actorlib (avoid duplications between cores) 2015-04-27 15:05:40 +02:00
Florent Kermarrec 5a930fe7cf lite* cores: changes permissions (+x) on make.py files and on litepcie init.sh file 2015-04-18 08:51:59 -04:00
Florent Kermarrec 341f635a85 litescope: add PCIe driver (mmap/Sysfs) and use it on litepcie example design 2015-04-18 13:58:20 +02:00
Florent Kermarrec 602eaf69c7 litepcie: fix asciiart in make.py 2015-04-17 14:10:32 +02:00
Florent Kermarrec b4b37fb10e litepcie: add linux driver + utilities (sysfs + dma) 2015-04-17 13:48:34 +02:00
Florent Kermarrec d22d58c7cc add litepcie core 2015-04-17 13:45:01 +02:00