1c82b20fcb
Merge pull request #1161 from stffrdhrn/or1k-marocchino
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marocchino: Add initial support for new OpenRISC core
2022-01-17 08:59:30 +01:00
672d1dd741
build/xilinx/symbiflow: Align devices.
2022-01-17 08:17:04 +01:00
4a3cd561c4
Merge pull request #1165 from bl0x/digilent_cmod_a7
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digilent_cmod_a7: Add xc7a35tcpg236-1 symbiflow_device.
2022-01-17 08:12:10 +01:00
4aff26ccaf
tools/litex_json2dts_linux.py: add mmc voltage regulator
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Add MMC voltage regulator, and reference it from the mmc node.
For now, all boards we know of provide a 3.3V fixed voltage to
their SDCard receptacles, either directly or via PMOD.
2022-01-16 19:53:36 -05:00
1011b817c8
bios/boot: fix width of sata `length` variable
2022-01-16 19:46:19 -05:00
27ccb3e776
cpu/serv: Add intial MDU support (mdu variant).
2022-01-16 19:58:09 +01:00
881d457fbe
digilent_cmod_a7: Add xc7a35tcpg236-1 symbiflow_device.
2022-01-16 12:15:50 +01:00
5992e1db8c
marocchino: Add initial support for new OpenRISC core
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The Marocchino is a superscaler OpenRISC implementation which has
advanced features including 64-bit double FPU support.
Much of the python module here is copied form mor1kx like the *.S
and *.h files.
2022-01-15 07:30:46 +09:00
c3b94a347e
cpu/rocket: increase IRQ lines to 8
2022-01-14 17:08:15 -05:00
cdacba06d1
soc/add_spi_sdcard: Fix missing renaming when rst pin is present.
2022-01-14 19:16:31 +01:00
ffc96a5655
Merge pull request #1155 from tongchen126/master
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litex/soc/software/bios/cmds/cmd_mem.c: add mem_cmp
2022-01-14 19:02:16 +01:00
96a9495d6a
soc/add_spi_sdcard: Add optional Tristate.
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This is required on some boards where the SDCard is shared with other chips (ex ESP32 on ULX3S).
2022-01-14 15:01:13 +01:00
4475b978d5
Merge pull request #1159 from fjullien/fix_cmd_mem_write
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bios: fix mem_write address increment
2022-01-14 13:53:41 +01:00
8f1d50525d
bios: fix mem_write address increment
2022-01-14 13:16:02 +01:00
1b9bdc57ac
litex/soc/software/bios/cmds/cmd_mem.c: add mem_cmp
2022-01-12 12:09:00 +08:00
add2746a54
tools/litex_cli: Rename wb to bus.
2022-01-11 14:54:18 +01:00
a8de9054a3
tools/litex_client: Allow passing CSR name to --read/--write to simplify use.
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ex:
litex_cli --read ctrl_scratch
litex_cli --write ctrl_scratch 0x5aa55aa5
2022-01-11 14:53:09 +01:00
a330e9fda5
cores/spi_flash: Deprecate SPI Flash MMAPed cores (Designs have been switched with LiteSPI).
2022-01-07 19:08:03 +01:00
30a99582ae
litex/compat: Fully deprecate up5kspram renaming. (Warning to suggest change has been here for > 1 year).
2022-01-07 18:40:12 +01:00
c46824153d
litex/compat: Fully deprecate soc_sdram (Warning to suggest change has been here for > 1 year).
2022-01-07 18:38:56 +01:00
c010a98719
cpu: Add default set_reset_address function to CPU that will be overrided by each CPU (avoid hasattr check).
2022-01-07 15:17:37 +01:00
cb13f71b56
build/openocd/stream: Add get_ir method and use it to compute IR and handle specific ECP5 case.
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JTAG-UART/JTAGBone on ECP5 non longer requires --jtag-chain=49 command.
2022-01-07 11:39:05 +01:00
f404877353
soc/SoCBusHandler: Add io_regions_check attribute and and disable IO region check with CPUNone.
2022-01-07 10:47:47 +01:00
e0961d7cb1
cores/cpu: Add missing Gowin EMCU comment.
2022-01-07 10:46:58 +01:00
23214638e4
cores/cpu: Allow multiple calls to set_reset_address (= override) since reset_adress is not not necessarily known at SoC creation.
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When booting from SPI Flash, things will be done in the following order:
- SoC creation.
- SPI Flash peripheral creation (with dynamic mapping).
- CPU reset address can then be set.
2022-01-07 09:07:34 +01:00
5c278ae437
cpu/rocket/core: Move IO Region (ROM/SRAM can't be in an IO Region).
2022-01-06 15:32:31 +01:00
23b9d73354
integration/soc: Improve mem_map overriding display.
2022-01-06 13:46:21 +01:00
5363d61859
Merge pull request #1151 from fjullien/fix_wb_slave_cache_configuration
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soc: raise an error if adding a SoCRegion with incoherent cache configuration
2022-01-06 10:12:20 +01:00
330144021b
soc: raise an error if adding a SoCRegion with incoherent cache configuration
2022-01-06 09:55:53 +01:00
153f9e9f6c
integration/builder: Use custom Formatter settings to improve readibility and minor cleanups.
2022-01-05 19:23:06 +01:00
1279ebebe8
build: Create toolchain parser group to improve --help readibility and cleanup.
2022-01-05 18:53:43 +01:00
0c1f0b17b4
integration/soc_core: Create soc parser group to improve --help readibility.
2022-01-05 18:30:04 +01:00
ec75228a72
builder: Create builder parser group to improve --help readibility.
2022-01-05 18:29:38 +01:00
67fa433efa
tools: Switch most the tools to argparse.ArgumentDefaultsHelpFormatter and uniformize help style.
2022-01-05 16:04:31 +01:00
54a137ef9f
builder: Use argparse.ArgumentDefaultHelpFormatter to automatically show default in help.
2022-01-05 16:03:38 +01:00
6f3f695d61
tools/litex_sim: Minor cleanups.
2022-01-05 15:20:27 +01:00
c424e51df4
litex_setup: Improve script status prints.
2022-01-05 14:52:21 +01:00
a6e2a529dc
litex_setup: Add initial installs config support (minimal, standard, full).
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Can be selected with --config=minimal/standard/full. This avoid installing all the
CPUs when only the popular ones will be used. Installation can be updated later
and switched to full installation with --config=full.
2022-01-05 13:56:35 +01:00
04e73b2e33
litex_setup.py: Switch git clone to git@github.com URLs when in --dev mode.
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Simplify dev/maintenance.
2022-01-05 10:07:35 +01:00
ba79224939
Bump year.
2022-01-05 09:21:08 +01:00
3fde251216
CHANGES: Set release date.
2022-01-05 08:53:10 +01:00
e21044641e
cores/cpu/vexriscv_smp: Force wishbone_memory mode when no direct memory_buses.
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This ensures a path for memory accesses will be created LiteDRAM is not used (ex with an HyperRAM memory).
2022-01-04 15:16:31 +01:00
f04a3dcc50
CHANGES: List changes since 2021.08.
2022-01-03 19:29:05 +01:00
c6dff1ea7e
Merge pull request #1141 from sergachev/zynq7000_bios
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Zynq7000 ARM BIOS support
2022-01-03 17:57:40 +01:00
3b05fa57d4
Merge pull request #1140 from sergachev/cleanup_defaults
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argparse: deduplicate defaults in help messages
2022-01-03 14:59:19 +01:00
79d0f0a893
interconnect/wishbone/axi: Automatically get InterconnectShared's shared data_width from first master.
2022-01-03 14:53:06 +01:00
90c204e87f
Merge pull request #1148 from tongchen126/master
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soc/software/bios/cmds/cmd_mem.c: fix number of required params
2022-01-03 14:40:39 +01:00
a8c8e4e3cf
litex/soc/interconnect/wishbone.py: add data_width param
2021-12-31 13:27:27 +08:00
e87e7ff31c
soc/software/bios/cmds/cmd_mem.c: fix number of required params
2021-12-30 20:43:05 +08:00
8ac3fbc039
soc/cores/led: Split LED-SHIFT in LED-READ/LED-SHIFT, simplify and fix off by one error.
2021-12-27 14:06:04 +01:00
enjoy-digital
Gabriel Somlo
Bastian Löher
Stafford Horne
Franck Jullien
tongchen126
Franck Jullien