e50ff33c6e
test/test_cpu: Disable Minerva test for now.
2021-12-13 16:51:23 +01:00
12d53790a9
test/test_cpu: Prepare microwatt/lm32 test.
...
microwatt: Still requires Yoys/GHDL-Synth installation.
lm32: Still requires prebuilt toolchain.
2021-10-26 16:37:38 +02:00
e617f52e34
test/test_cpu: Comment test_mor1kx for now (test work but issue seems related to the pre-built toolchain).
2021-10-26 16:30:02 +02:00
cb9f0fb1b0
ci/test_cpu: Install OpenRISC GCC toolchain in CI and add mor1kx to test_cpu.
2021-10-26 15:45:43 +02:00
71a91eac15
test: Rename test_boot.py to test_cpu.py.
2021-10-26 08:35:16 +02:00
47b3c9bc08
soc/interconnect/packet: Remove last_be support in LiteX, specialized Packetizer/Depacketizer have been moved to LiteEth to simplify development and avoid eventual regresion on others cores.
...
As seen during the last LiteEth developments, last_be data qualifier is not easy to handle correctly and should be replaced by a simpler data qualifier (similar to AXI's tkeep/tstrb). It will
be easier to do so by having a local copy of Packetizer/Depacketizer directly in LiteEth (still with last_be support) and work on the simpler data qualifier in LiteX (and test it on LitePCIe).
2021-10-25 11:17:36 +02:00
2886fe1701
Add bios test mode for CI ( #1076 )
...
* Add bios test mode for CI
This enables to test the booting of each CPU configurations with the bios in Verilator simulation.
2021-10-24 12:08:58 +02:00
8e448592f0
interconnect/packet: Revert old last/ready logic handling (new one breaks test_packet) and comment out test_packet2 tests (does not seems to be working with previous last/ready handling).
2021-10-23 18:21:47 +02:00
59fd2d31c7
test/test_packet2: Fix imports.
2021-10-23 17:54:00 +02:00
32bb2554bc
test: Rename new test_packet/stream to test_packet2/stream2 and revert old tests.
...
Old and new tests are complementary and would need to be merged.
2021-10-23 17:40:41 +02:00
434b3a3654
Merge pull request #1008 from lschuermann/dev/packetizer-last_be-fix
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{Dep,P}acketizer: properly handle last_be wraparound
2021-10-23 17:33:29 +02:00
99f3498f2d
cores/icap/ICAP: Add Register read capability.
...
Useful to get some internal status, ex the IDCode or know if the executed bistream
in a multiboot configuration is the operational or fallback one.
2021-10-04 17:22:57 +02:00
3504904c09
cores/icap/ICAP: Rewrite using with an FSM instead of Timeline (will be easier to extend).
2021-10-04 15:06:03 +02:00
9416e30249
test/test_icap: Add IPROG sequence check.
2021-10-04 14:41:38 +02:00
cb2f2d7021
cores/icap/ICAP: Rewrite using constants and cleanup.
2021-10-04 14:25:40 +02:00
6733a3e3e6
clock/lattice_ecp5/ECP5PLL: ensure feedback path selected before exiting search
2021-09-15 00:07:43 -05:00
a568b7e26a
test_packet.py: test randomly generated headers
...
Also includes some fixes for the non-last_be test path such that the
expected behavior is the one currently oberserved with the Packetizer
and Depacketizer.
2021-09-10 15:30:05 +02:00
958bcaad2e
test_packet.py: add last_be tests
2021-09-10 12:30:04 +02:00
037294dc3b
test_packet.py: support passing debug_print parameter
2021-09-09 16:37:26 +02:00
6bda383178
test_packet.py: support {Dep,P}acketizer behavior without last_be
2021-09-09 16:37:26 +02:00
a08271b83a
test_packet.py: utilize generic stream_inserter/colletor interface
2021-09-09 16:08:12 +02:00
ca50cba986
Rewrite test_stream.py with reusable stream_inserter/collector
2021-09-09 16:08:12 +02:00
79ac09316a
interconnect/axi/AXIBurst2Beat: Fix BURST_WRAP case.
2021-08-06 16:41:58 +02:00
1ce48a973b
clock/lattice_ecp5: Fix and rework 4-output solver implementation.
...
The implementation was causing regressions on actual designs, rework done:
- Only keep a common iteration loop as before.
- Add iteration on CLKO dividers (to fall in the VCO range).
- Do the iterations as before, if while doing it we find a clock suitable for feedback: just use it.
- If no feedback clock has been found: create it (if at least one free output available, if not raise an error).
2021-07-26 14:00:00 +02:00
8954041a93
clock/lattice_ecp5/ECP5PLL: Only consider non-dpa clocks as feedback
...
Dynamically adjusting the phase of a feedback will cause it to unlock.
The phase adjust ports are shared by all the outputs, so there is no
technical way to prevent this. Allow the user to indicate that they
will not adjust a clock when requesting an output by setting
uses_dpa=False, and only consider those that the user has promised not
to use.
2021-07-08 08:14:14 -05:00
f6b2135cc9
test/test_timer: Update.
2021-05-27 19:37:51 +02:00
675349055b
inteconnect/stream: Increase io_lcm size when io_lcm/i_dw or io_lcm/o_dw < 2.
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Allow supporting all cases.
2021-03-18 13:47:10 +01:00
98b75d8671
Add initial core test for Timer
2021-01-21 21:37:41 -06:00
f31f9a20f0
boards: remove and switch to litex_boards.
...
Keeping board definition files directly in LiteX is no longer useful since we are already relying on board
definitions files from LiteX-Boards (https://github.com/litex-hub/litex-boards ) in various benches/projects
and having definitions files directly in LiteX creates confusion/additional work.
For projects using board definition files from LiteX, the litex.boards import can just be replaced with litex_boards:
from litex.boards.platforms import kc705
from litex_boards.platforms import kc705
2021-01-04 14:09:35 +01:00
6771ed0796
ci: migrate from Travis CI to Github Actions.
2020-11-24 15:55:49 +01:00
cecb36d608
test/test_clock: update with new supported devices.
2020-11-09 10:37:20 +01:00
e91ec2ed83
soc/cores/code_8b10b: add StreamEncoder/Decoder (to be used with LiteX's streams).
...
With improvements to handle backpressure on non-continous streams.
2020-10-21 09:29:21 +02:00
305092c7b8
test/test_icap: update.
2020-10-07 12:36:08 +02:00
f7b6dd05ae
cores/clock: add initial Xilinx Ultrascale Plus PLL/MMCM/IDELAYCTRL support.
2020-09-03 18:58:10 +02:00
77ae243310
test: add SPDX License identifier to header and specify file is part of LiteX.
2020-08-23 15:40:21 +02:00
a5d0a340c3
test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces.
2020-08-04 09:39:23 +02:00
e78d950a31
soc/interconnect/axi: add AXILite -> AXI converter
2020-07-30 13:50:34 +02:00
879e6ffe73
soc/interconnect/axi: add basic AXI Lite up-converter
2020-07-24 13:47:18 +02:00
32160e615f
soc/interconnect/axi: separate AXI Lite converter channels
2020-07-24 09:25:57 +02:00
a9d8b81385
test/axi: move all AXI Lite tests to separate file
2020-07-22 17:16:33 +02:00
8ae501c391
test/axi: add crossbar stress tests
2020-07-22 17:16:33 +02:00
32d9e212c5
soc/interconnect/axi: improve Timeout module and test it with shared interconnect
2020-07-22 17:16:33 +02:00
2cab7fbf0f
test/axi: add shared AXI Lite interconnect tests
2020-07-22 17:16:33 +02:00
3a08b21d44
soc/interconnect/axi: implement AXI Lite decoder
2020-07-22 17:16:33 +02:00
214cfdcaeb
soc/interconnect/axi: lock AXILiteArbiter until all requests have been responded to
2020-07-22 17:16:33 +02:00
baf23c9c9b
test/test_axi: add AXI Lite interconnect arbiter tests
2020-07-22 17:16:29 +02:00
f47ccdae99
soc/interconnect/axi: point-to-point interconnect and timeout module with tests
2020-07-22 17:16:12 +02:00
47ce15b431
interconnect/wishbone: add minimal UpConverter.
2020-07-21 19:35:14 +02:00
100aa5a4ca
soc/cores/spi/SPIMaster: rewrite/simplify.
...
- Make sure MOSI is latched on start, MISO is stable during Xfer (last value).
- Allow clk_divider down to 2.
- improve test errors reporting with hex() on AssertEqual.
2020-07-20 10:44:18 +02:00
93bcc94b53
soc/interconnect/axi: implement AXILite down-converter
2020-07-16 17:02:49 +02:00
Florent Kermarrec
Navaneeth Bhardwaj
George Hilliard
Leon Schuermann
Blake Smith
Jędrzej Boczar