c03c41eb77
litescope: rename host directory to software (to be coherent with others cores)
2015-05-01 20:45:02 +02:00
a8b8af220a
liteusb: add basic wishbone frontend (We could also reuse Etherbone in the future)
2015-05-01 20:44:59 +02:00
cd3a51ada6
litescope: fix missing source ack on LiteScopeWishboneBridge
2015-05-01 20:44:57 +02:00
1281a463d6
litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
...
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
23126415d3
litescope: use full name in io.py
2015-05-01 17:49:31 +02:00
23ba1ccb52
targets/minispartan6: add USBSoC (working, should also be usable on pipistrello)
2015-05-01 16:22:45 +02:00
da0fe2ecfb
liteusb: refactor software (use python instead of libftdicom in C) and provide simple example.
...
small modifications to fastftdi.c are also done to select our interface (A or B) and mode (synchronous, asynchronous)
2015-05-01 16:22:26 +02:00
603b4cdc8c
liteusb: continue refactoring (virtual UART and DMA working on minispartan6)
...
- rename ft2232h phy to ft245.
- make crc optional
- fix depacketizer
- refactor uart (it's now only a wrapper around standard UART)
- fix and update dma
2015-05-01 16:11:15 +02:00
8aa3fb3eb7
com/uart: add tx and rx fifos.
...
Since ressource usage is low with default depth of 16 (implemented in RAM LUTs) we don't keep old behaviour.
Tested successfully with BIOS and flterm.
2015-05-01 15:59:26 +02:00
70bc4ecb59
mibuild/platforms/pipistrello: add _n suffix to usb fifo pins
2015-05-01 15:49:33 +02:00
aea7308051
mibuild/platforms/minispartan6: rename ftdi_fifo to usb_fifo and fix rd_n/wr_n swap
2015-05-01 15:48:42 +02:00
01e2343978
doc: remove cordic
2015-05-01 14:07:38 +08:00
96bff77c36
add examples tests
2015-05-01 00:50:17 +08:00
a6f290ac16
liteusb: add ft2232h_sync_tb
2015-04-28 19:05:34 +02:00
28c50112a4
liteusb: add FT2232HPHYAsynchronous PHY (Minispartan6+, Pipistrello), needs more simulations and on-board tests
2015-04-28 19:01:03 +02:00
30eed19283
liteusb: continue refactoring and add core_tb (should be almost OK)
2015-04-28 18:58:38 +02:00
7fc96da51c
misoclib/com/uart: remove liteeth dependency (copy/paste error)
2015-04-28 18:53:46 +02:00
d253adee61
liteeth: use Migen's Packetizer/Depacketizer, remove generic and move etherbone/tty to frontend
2015-04-28 18:51:40 +02:00
1cbc468bda
migen/actorlib/packet: add Packetizer and Depacketizer
2015-04-28 18:44:05 +02:00
0da9311d70
migen/genlib: avoid use of floating point in reverse_bytes
2015-04-27 21:04:18 +02:00
453279a7c8
litesata: cleanup link
2015-04-27 15:33:01 +02:00
0c08055014
Merge branch 'master' of https://github.com/m-labs/misoc
2015-04-27 15:28:08 +02:00
dc8d844579
liteusb: begin refactoring and simplification (wip)
2015-04-27 15:22:49 +02:00
3ce5ff3722
migen/actorlib: add packet.py to manage dataflow packets (Arbiter, Dispatcher, Header definitions, Buffer)
2015-04-27 15:14:38 +02:00
f976b1916a
migen/actorlib/misc: add BufferizeEndpoints
...
BufferizeEndpoints provides an easy way improve timings of chained dataflow modules and avoid polluting code with internals buffers.
2015-04-27 15:12:01 +02:00
e96ba1e46f
migen/genlib/misc: add reverse_bytes
2015-04-27 15:08:10 +02:00
91c77d464c
liteeth: use new Migen modules from actorlib (avoid duplications between cores)
2015-04-27 15:06:37 +02:00
20dd6d3047
litepcie: use new Migen modules from actorlib (avoid duplications between cores)
2015-04-27 15:05:40 +02:00
1ef81c4d24
litesata: split hdd model (phy, link, transport, command & hdd) and update simulations
2015-04-27 14:51:03 +02:00
ded3f22574
litesata: use new Migen modules from actorlib/packet.py (avoid duplications between cores)
2015-04-27 14:48:14 +02:00
fe867ccf33
litesata: remove icarus_workaround.patch (obsolete)
2015-04-27 14:44:54 +02:00
1d9771f574
spiflash: use SoC defines, add write_to_flash function
2015-04-27 13:42:32 +08:00
0b1a2e1022
liteeth: do MII/GMII detection in gateware for gmii_mii phy
2015-04-26 18:08:07 +02:00
07b7c2a13f
liteeth/phy/gmii: add default value for pads_register
2015-04-26 14:54:54 +02:00
ae71bf2830
liteeth: fix and improve 10/100/1000Mbps speed auto detection
2015-04-26 14:54:53 +02:00
472665b81d
Add a command line option (-use_new_parser yes) to Xilinx XST to force use of the newer parser for older FPGAs.
2015-04-25 23:01:07 +08:00
73a1687562
migen/test: for now desactivate test_generic_syntax (travis-ci's Verilator needs to be upgraded?)
2015-04-24 13:24:52 +02:00
67702f25ab
migen/fhdl/verilog: _printheader/_printcomb, remove default value of arguments which are not used in internal functions. (thanks sb)
2015-04-24 12:54:08 +02:00
bc30fc57e7
migen/fhdl: give explicit names to syntax specialization when asic_syntax is used
2015-04-24 12:14:14 +02:00
61c3efc5f5
migen/test: rename asic_syntax to test_syntax and simplify
2015-04-24 12:00:46 +02:00
130fd19dec
liteeth/core/ip: simplify ip rx checksum control
2015-04-24 11:31:10 +02:00
5b48e7bb52
liteeth: finish with_preamble_crc vs with_hw_preamble_crc renaming
2015-04-24 11:30:35 +02:00
2d56d32009
liteeth/mac/core: simplify and fix padding
2015-04-24 09:36:33 +02:00
b93df693a4
travis: add conda package generation and upload + build doc
2015-04-23 14:15:31 +08:00
7280bdb9d4
Add conda recipe for Migen
2015-04-23 14:15:15 +08:00
2f45d4640b
doc: fix warnings during doc build
2015-04-23 12:34:17 +08:00
e5b170f02d
travis: install verilator
2015-04-22 12:30:03 +08:00
7ec0ecae11
test: add test for asic_syntax
2015-04-22 12:29:07 +08:00
6b5969732a
add Travis CI badge
2015-04-22 12:20:46 +08:00
28dde1e38f
fhdl/verilog: add flag to produce ASIC-friendly output
2015-04-21 09:52:14 +08:00
Florent Kermarrec
Sebastien Bourdeauducq
Alain Péteut
William D. Jones
Yann Sionneau
Guy Hutchison