The current check compares the integers split out from `meson --version`
one by one. This is an ad-hoc version comparison algorithm with a few
flaws, notably that it doesn't truly understand how version components
fit together, and that broke once Meson bumped the major version. There
are other potential issues that could show up but haven't yet, such as
versions with words in them (release candidates).
The packaging module is a high-quality library that provides a standard
version parsing algorithm, with which you can simply say "is this
version object greater than that one". Use it instead.
Fixes#1545
a286d77e introduced a bug, where `-include_dirs` parameter is
incorrectly defined.
Following TCL code is being generated:
```tcl
synth_design -directive default -top digilent_arty -part xc7a35ticsg324-1L -include_dirs \{.join(self.platform.verilog_include_paths)}\}
```
Below is an explanation why it didn't work:
Python's f-strings escape curly braces using double curly braces like so
`{{` instead of using backslash `\{`.
What's more, you need to alternate single and double quotations marks
when using strings in curly braces expression otherwise two string
objects are being generated and errors like this one can happen.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
Copy all feature and performance related CSR configuration from
sun20i_d1_spl, which are values Allwinner suggests for D1 SoC.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Boards such as the Xilinx VC707, STLV7325, etc. offer support for
dual-rank memory, which results in a 512-bit wide native LiteDRAM
port. These additional "8x wide" (or "octo") variants support that
width directly, without the need for additional data width conversion
that whould have to be implemented on the LiteX side of the SoC.
Suggested-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
CPUs with a dedicated memory port (MemBus) are typically connected
directly to the LiteDRAM port. Some models (e.g., Rocket) come in
(otherwise equivalent) variants specifically pre-generated to fit
the various "standard" LiteDRAM port widths (so far, 64, 128, or
256 bits).
This patch introduces a warning when the CPU variant's dedicated
MemBus doesn't exactly match the width of LiteDRAM, requiring
explicit conversion.
The goal is to inform the user and provide them with an opportunity
to pick a more suitable CPU variant (of matching MemBus width), if
available.
enjoy-digital
stone3311
Eli Schwartz
Michal Sieron
Navaneeth Bhardwaj
Tomasz Michalak
Jevin Sweval
Gwenhael Goavec-Merou
Icenowy Zheng
Richard Tucker
Gabriel Somlo
Dolu1990