Sebastien Bourdeauducq
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cef1c5d3af
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record: better exception code
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2012-01-09 15:17:24 +01:00 |
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Sebastien Bourdeauducq
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89bf704b2b
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record: preserve order
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2012-01-09 15:14:42 +01:00 |
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Sebastien Bourdeauducq
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bdcaeb159b
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flow: draw network graph
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2012-01-09 14:21:54 +01:00 |
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Sebastien Bourdeauducq
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d26ded93d8
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flow: actor busy signal
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2012-01-09 14:21:45 +01:00 |
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Sebastien Bourdeauducq
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d2d55372d8
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Composer (WIP)
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2012-01-08 13:56:11 +01:00 |
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Sebastien Bourdeauducq
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34c69db14a
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endpoint: add _i/_o suffix on signal names
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2012-01-07 21:21:46 +01:00 |
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Sebastien Bourdeauducq
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cdd9977a40
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fhdl: better signal naming heuristic
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2012-01-07 15:30:14 +01:00 |
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Sebastien Bourdeauducq
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b6763c28ea
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constant: equality
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2012-01-07 12:29:47 +01:00 |
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Sebastien Bourdeauducq
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7b395b565e
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verilog: split comb block, use assign statements
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2012-01-07 12:19:06 +01:00 |
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Sebastien Bourdeauducq
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f209bf6b33
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convtools -> tools
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2012-01-07 00:39:28 +01:00 |
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Sebastien Bourdeauducq
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0b195a244d
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flow: network
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2012-01-07 00:33:28 +01:00 |
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Sebastien Bourdeauducq
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3c1dada9cf
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record: compatibility check
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2012-01-06 23:00:23 +01:00 |
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Sebastien Bourdeauducq
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588f1a259e
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flow: plumbing
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2012-01-06 17:24:05 +01:00 |
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Sebastien Bourdeauducq
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8f1bf508ca
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actor: simplified automatic control
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2012-01-06 15:35:17 +01:00 |
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Sebastien Bourdeauducq
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a3bf877802
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ALA: use records for tokens
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2012-01-06 14:32:00 +01:00 |
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Sebastien Bourdeauducq
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1905eb3707
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README: update copyright year
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2012-01-06 14:15:57 +01:00 |
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Sebastien Bourdeauducq
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038992e7d2
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corelogic: record
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2012-01-06 11:20:44 +01:00 |
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Sebastien Bourdeauducq
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d7a3bed44c
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Signal repr
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2012-01-06 11:20:33 +01:00 |
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Sebastien Bourdeauducq
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4c040810bc
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Merge branch 'master' of github.com:milkymist/migen
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2012-01-05 19:27:55 +01:00 |
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Sebastien Bourdeauducq
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b60abfaa4a
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Convert -> convert
|
2012-01-05 19:27:45 +01:00 |
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Sebastien Bourdeauducq
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9366a226bb
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Convert -> convert
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2012-01-05 19:27:33 +01:00 |
Alain Péteut
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6bd8566c48
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setup.py: fix to catch all modules
Signed-off-by: Alain Péteut <peteut@space.unibe.ch>
|
2011-12-27 11:19:37 +01:00 |
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Alain Péteut
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5f53e6473a
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Add setup script
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2011-12-24 13:46:40 +01:00 |
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Sebastien Bourdeauducq
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1ce4fbdb98
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example: flow conversion
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2011-12-23 00:36:07 +01:00 |
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Sebastien Bourdeauducq
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edf90870c2
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flow: sum and division actors
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2011-12-23 00:35:53 +01:00 |
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Sebastien Bourdeauducq
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76db20cd9f
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fhdl: encapsulate replicated constants
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2011-12-23 00:35:13 +01:00 |
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Sebastien Bourdeauducq
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f0aac4b50f
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flow: actor class
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2011-12-22 19:37:16 +01:00 |
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Sebastien Bourdeauducq
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566295dea3
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csr: use optree
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2011-12-22 19:36:56 +01:00 |
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Sebastien Bourdeauducq
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ba40f58491
|
corelogic: operator tree
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2011-12-22 15:46:19 +01:00 |
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Sebastien Bourdeauducq
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8a394f9159
|
verilog: comb reset
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2011-12-22 00:04:53 +01:00 |
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Sebastien Bourdeauducq
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4d6be55e9f
|
verilog: break down Convert function
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2011-12-21 23:08:50 +01:00 |
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Sebastien Bourdeauducq
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26e0b817e8
|
verilog: ignore variable property in combinatorial block
|
2011-12-21 23:00:36 +01:00 |
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Sebastien Bourdeauducq
|
7456195775
|
Consistent names
|
2011-12-21 22:57:07 +01:00 |
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Sebastien Bourdeauducq
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47d321cd75
|
README: Flow
|
2011-12-20 00:07:46 +01:00 |
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Sebastien Bourdeauducq
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d9dc604c99
|
README: Core Logic, Bus, Bank
|
2011-12-19 23:24:31 +01:00 |
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Sebastien Bourdeauducq
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7774ace7e1
|
README: structure + FHDL description
|
2011-12-19 22:15:10 +01:00 |
|
Sebastien Bourdeauducq
|
3b640c45bb
|
Use new syntax
|
2011-12-18 22:02:05 +01:00 |
|
Sebastien Bourdeauducq
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af0a03b65f
|
examples: remove old-style declarations
|
2011-12-18 21:54:39 +01:00 |
|
Sebastien Bourdeauducq
|
94c5fba067
|
corelogic: fix signal exports
|
2011-12-18 21:54:28 +01:00 |
|
Sebastien Bourdeauducq
|
4f4d809a4e
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fhdl: better matching of assignment
|
2011-12-18 21:49:48 +01:00 |
|
Sebastien Bourdeauducq
|
107f03fd4b
|
Remove uses of declare_signal
|
2011-12-18 21:47:48 +01:00 |
|
Sebastien Bourdeauducq
|
dd42b2daff
|
fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal
|
2011-12-18 21:47:29 +01:00 |
|
Sebastien Bourdeauducq
|
41e2430e2b
|
fhdl: automatic signal name from assignment
|
2011-12-18 21:26:51 +01:00 |
|
Sebastien Bourdeauducq
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6664af73d1
|
uart: new design using FHDL and bank (TX only, incomplete)
|
2011-12-18 00:29:37 +01:00 |
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Sebastien Bourdeauducq
|
135a2eb868
|
bank: support raw registers
|
2011-12-18 00:28:04 +01:00 |
|
Sebastien Bourdeauducq
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d21e095397
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fhdl: fix series of if/elif/else
|
2011-12-17 20:31:42 +01:00 |
|
Sebastien Bourdeauducq
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1a845d4553
|
32-device, 8-bit CSR bus
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2011-12-17 15:54:49 +01:00 |
|
Sebastien Bourdeauducq
|
bb21f7584a
|
32-device, 8-bit CSR bus
|
2011-12-17 15:54:42 +01:00 |
|
Sebastien Bourdeauducq
|
1b3edd07ca
|
norflash tb: use get_fragment
|
2011-12-17 15:22:26 +01:00 |
|
Sebastien Bourdeauducq
|
6f8a6db40a
|
verilog: get the simulator to run the combinatorial process at the beginning
|
2011-12-17 15:20:22 +01:00 |