Florent Kermarrec
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745d83a332
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boards: add initial NeTV2 support (clocks, leds, dram, ethernet)
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2019-05-10 18:55:40 +02:00 |
|
Florent Kermarrec
|
3ee9ce0529
|
test/test_targets: fix test_ulx3s name
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2019-05-09 11:48:57 +02:00 |
|
Florent Kermarrec
|
74d37465b3
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test/test_targets: comment bad variant tests for now
|
2019-04-29 17:11:42 +02:00 |
Tim 'mithro' Ansell
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5cbc5bc199
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Adding testing of cpu variants.
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2019-04-26 18:57:49 -05:00 |
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Florent Kermarrec
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f7c0b118ce
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test/test_targets: cover all platforms
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2019-04-23 11:38:18 +02:00 |
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Florent Kermarrec
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7d278854d5
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global: switch to VexRiscv as the default CPU
VexRiscv can now replace LM32 for almost all usecases and we now have better
software support with RISC-V.
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2019-04-22 09:41:07 +02:00 |
|
Florent Kermarrec
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28d80bd641
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ci: fix test_targets/test_simple
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2019-04-22 08:53:43 +02:00 |
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Florent Kermarrec
|
e98ac680c1
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travis: simplify, enable and add RISC-V toolchain to build targets
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2019-04-22 08:32:00 +02:00 |
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Florent Kermarrec
|
68e1dfca28
|
boards: avoid duplicating platforms that can be found in migen/litex-buildenv
The platforms that are kept are the ones used for litex development.
|
2019-01-06 19:01:19 +01:00 |
|
Florent Kermarrec
|
5137c2bf88
|
test/test_targets: update
|
2018-11-17 17:36:57 +01:00 |
|
Florent Kermarrec
|
0b0e3ac1dd
|
test/test_targets: test simple design with all platforms
|
2018-09-24 02:02:14 +02:00 |
|
Florent Kermarrec
|
e04530e0c4
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test/test_targets: update and reorganize targets
|
2018-09-24 01:15:33 +02:00 |
|
Florent Kermarrec
|
1925ba176f
|
replace litex.gen imports with migen imports
|
2018-02-23 13:38:19 +01:00 |
|
Florent Kermarrec
|
b4ebfb4031
|
test/test_targets: check top.v generation
|
2017-04-24 19:25:58 +02:00 |
|
Florent Kermarrec
|
35e3d93d9b
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test: add basic test_targets.py
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2017-04-24 19:13:17 +02:00 |