04f6b17d03
build: Remove openfpga build backend (Replaced by osfpga build backend).
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OpenFPGA build backend was an experimental build backend for OpenFPGA/SOFA chips.
OpenFPGA is now providing a new FOEDAG build framework abstracting things and providing
a regular .tcl/.sdc based toolchain.
2022-05-18 15:36:30 +02:00
aaf03b3860
soc/add_sata: Integrate LiteSATAIdentify module.
2022-05-18 15:27:13 +02:00
5df1f5f511
soc/add_sata: Add IRQ support.
2022-05-18 15:05:00 +02:00
5c617d139c
Add initial CVA5 support
2022-05-17 20:19:17 -04:00
4401b5a5e8
build/osfpga: Remane FOEDAGToolchain to OSFPGAToolchain and add Foedag/Raptor support through toolchain parameter.
2022-05-17 19:42:26 +02:00
f16f8e5f9e
software/demo/README: Update --build-path (Thanks @mzau).
2022-05-17 19:25:11 +02:00
4810cc15da
soc/LiteXSoCArgumentParser: Fix --cpu-type parsing.
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Could still be improved.
2022-05-17 19:15:06 +02:00
71a5ef2380
build: Add initial OSFPGA/FOEDAG build backend and blinky example.
2022-05-16 16:26:27 +02:00
b020d4cf62
cores/video/VideoTerminal: Avoid downloading font is present locally.
2022-05-12 16:08:42 +02:00
7e1d2bdf9b
cores/video/VideoHDMIPHY: Rework Fake Differential support and automatically detect when required.
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- Detect activation from passed pads: If p and n present -> Activate.
- Make code a bit more generic to avoid if/else.
- Keep change self contained to VideoHDMIPHY to avoid propagating features to VideoHDMI10to1Serializer.
(Less optimal in term of resources since doubling the serializers, but should be negligible and we are
fixing a hardware issue here...).
2022-05-12 16:07:31 +02:00
8fd96cab84
Merge pull request #1290 from swetland/hdmi
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cores/video: VideoHDMIPHY: enable driving both + and - diff outs
2022-05-12 15:08:45 +02:00
50830da636
tools/litex_sim: Use LiteXSoCArgumentParser.
2022-05-12 11:56:33 +02:00
aa8932dd4f
integration/builder/soc: Add get_build_name method (Useful now that builder is no longer called automatically without --build).
2022-05-12 11:56:08 +02:00
e451a87617
cpu/rocket: add 1-core full (fpu) wide-bus variants
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- 1-core "full" (fpu-enabled) variants with double, quad mem. bus width
2022-05-10 19:35:51 -04:00
479773418d
tools/litex_soc_gen: Add identifier, move wb_region to IOs and add optional debug.
2022-05-10 15:16:58 +02:00
48b523cf7e
add cva6 cpu
2022-05-09 21:12:08 +02:00
51c5438c11
cpu/firev: Make name consistent with other CPUs.
2022-05-09 18:23:53 +02:00
7f703dd18f
Merge pull request #1293 from enjoy-digital/fhdl_namer_changes
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FHDL Namer integration and memory .init naming improvements.
2022-05-09 18:22:42 +02:00
6d36fd2dda
gen/fhdl/namer: Minor cleanup to ease readability.
2022-05-09 17:53:27 +02:00
974d15d8c0
Merge pull request #1292 from zeldin/vexriscv_crt_fix
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cpu/vexriscv: Fix compilation of crt0.S with new binutils.
2022-05-09 14:22:49 +02:00
2db57d4be3
interconnect: Add name parameter to Wishbone/AXI SRAMs nad use it in add_ram to improve generated memory names.
2022-05-09 10:29:15 +02:00
7370a9fe6f
fhdl/memory/namer: Improve readability.
2022-05-09 10:22:48 +02:00
a0f0ea4842
cpu/vexriscv: Fix compilation of crt0.S with new binutils.
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The csrw opcode is no longer part of the "I" instruction set but has
been moved to a separate extension. Enable that extension in crt0.S.
2022-05-08 18:54:23 +02:00
3a388d1f19
fhdl/memory: Prefix memory files with build name.
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This simplify re-integrating pre-generated SubSoCs in a top level SoC.
2022-05-06 20:21:30 +02:00
7800858c7a
gen/fhdl/namer: Cleanup & add comments on Namespace.
2022-05-06 20:07:35 +02:00
61eead5170
fhdl/memory/verilog: Rename ns -> namespace and minor cleanup.
2022-05-06 19:34:21 +02:00
b83e84c78a
gen/fhdl: Integrate namer from Migen to give us more flexibility on generated verilog names.
2022-05-06 16:04:24 +02:00
79d0e0916a
CHANGES: Update.
2022-05-06 15:16:48 +02:00
3f101a3520
CHANGES: Update.
2022-05-06 13:43:39 +02:00
a8c48b42f9
Merge pull request #1281 from antmicro/i2s_f4pga_fix
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Add LiteX equivalent of Xilinx FIFO_SYNC_MACRO to I2S
2022-05-06 09:10:22 +02:00
0a1ae7b413
setup.py: Expose litex_soc_gen and litex_periph_gen and sort console scripts.
2022-05-05 17:44:59 +02:00
e8b6200225
tools: Add initial LiteX standalone SoC generator.
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Allow generating standalone SoC with CPU/Peripherals that can be re-integrated in
external design or top level LiteX SoCs.
Example of of use:
python3 litex_soc_gen.py --cpu-type=vexriscv --bus-standard=wishbone --build
python3 litex_soc_gen.py --cpu-type=naxriscv --bus-standard=axi-lite --build
2022-05-05 17:36:34 +02:00
e7cee80670
tools/litex_gen: Rename to litex_periph_gen to make it more explicit (And also to prepare for litex_soc_gen).
2022-05-05 17:36:22 +02:00
36ea82546f
litex_setup: Allow specifying tag for --init --update.
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Allow installing from release tags, ex to install 2022.04 from scratch:
./litex_setup.py --tag=2022.04 --init --install --user.
To update to 2022.04 from a previous installation:
./litex_setup.py --tag=2022.04 --update
To update to latest (dev):
./litex_setup.py --updatelitex_setup: Allow specifying tag for --init --update.
2022-05-04 19:26:22 +02:00
a4cc859df0
CHANGES: Do 2022.04 release.
2022-05-03 13:09:30 +02:00
09e40f85da
cores/video: VideoHDMIPHY: enable driving both + and - diff outs
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Add a new parameter (drive_both), defaulting False, that will
drive data#_n as well as data#_p (and with the inverse of data#_p)
VideoHDMI10to1Serializer is similarly extended.
Existing users of these should be unaffected (tested that with
the Radiona ULX3S, which was not impacted).
2022-05-03 04:01:28 -07:00
17b6f792c7
tools/litex_client: Fix read/write when address is directly specified.
2022-05-03 10:05:04 +02:00
8f63a64a86
cores/hyperbus: Simplify #1288 and add parameter retro-compatibility.
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sys_clk_freq is set to 10e6 when passed to None.
2022-05-02 17:24:35 +02:00
25e7569cd1
Merge pull request #1288 from fjullien/hyperram_timeout
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Hyperram timeout and cyc
2022-05-02 16:30:58 +02:00
c12bdf5454
CHANGES: Update.
2022-05-02 14:18:12 +02:00
cd589846c4
CONTRIBUTORS: Update.
2022-05-02 14:01:41 +02:00
a66af6343e
hyperbus: check if cyc is active during every state
2022-04-28 23:05:58 +02:00
5220984df8
hyperbus: add a timeout for long bursts
2022-04-28 23:05:58 +02:00
d5878050b3
cores: i2s: Use FIFOSyncMacro if not built with Vivado
2022-04-27 10:53:52 +02:00
22abe1d543
Add tests for FIFOSyncMacro
2022-04-27 10:53:52 +02:00
c584cb3fa7
Add LiteX equivalent of Xilinx FIFO_SYNC_MACRO
2022-04-27 10:53:52 +02:00
665367fe67
Merge pull request #1284 from smunaut/bist-overflow
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fix overflow in BIST
2022-04-27 10:08:59 +02:00
6ec7a24731
software/liblitedram: Fixup overflow in BIST speed math
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With decent burst length, fast RAM and fast clock rate,
the intermediate result can easily overflow 32 bits.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-04-26 23:33:08 +02:00
3959ca39d4
Merge pull request #1282 from cklarhorst/master
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software/bios: Fix build error for targets with sdcard but without main_ram_base
2022-04-25 19:26:47 +02:00
63cda6c7b9
soc/add_ethernet: soc/add_etherbone: Add data_width parameter and allow 8-bit/32-bit core data_width.
2022-04-25 18:44:52 +02:00
Florent Kermarrec
Eric Matthews
Gabriel Somlo
Massimiliano Giacometti
Dolu1990
Marcus Comstedt
Brian Swetland
Franck Jullien
Robert Szczepanski
Sylvain Munaut