f33ea63278
Merge pull request #1316 from gsomlo/gls-printf-warning
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software/liblitesata: address printf int size warning
2022-06-02 21:29:39 +02:00
31439f7475
software/common.mak: Shorten GCC_INSTALLATION_PATH to GCC_PATH.
2022-06-02 18:41:55 +02:00
bafae4d449
soc/integration/export: Rewrite and fix zicsr RISC-V workaround.
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- Improve regex to be more robust (Was not working with binutils from Sifive).
- Improve readability.
- Only do it for RISC-V.
- Add comments.
2022-06-02 18:39:50 +02:00
9e38dc70a4
Merge pull request #1279 from xhebox/master
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support custom toolchain
2022-06-02 18:05:51 +02:00
e0f183c219
Merge pull request #1317 from Icenowy/gw2apll
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GW1NPLL: add GW2A
2022-06-02 17:32:35 +02:00
c66ba025f8
GW1NPLL: add GW2A
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GW2A has the same PLL primitive with GW1N.
Add support for it to GW1NPLL.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-06-02 21:19:41 +08:00
712bfe27ca
software/liblitesata: address printf int size warning
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uint32_t is treated as `unsigned int` by the 64-bit compiler, and
as `long unsigned int` by the 32-bit compiler. As such, we'll get
a warning on one or the other regardless of whether we use "%ld"
or "%d" with printf:
on 64-bit (rocket, using "%ld"):
./litex/litex/soc/software/liblitesata/sata.c: In function 'sata_init':
./litex/litex/soc/software/liblitesata/sata.c:87:45:
warning: format '%ld' expects argument of type 'long int', but
argument 2 has type 'uint32_t' {aka 'unsigned int'} [-Wformat=]
87 | printf("Capacity: %ldGB\n", capacity);
| ~~^ ~~~~~~~~
| | |
| | uint32_t {aka unsigned int}
| long int
| %d
on 32-bit (vexriscv, using "%d"):
./litex/litex/soc/software/liblitesata/sata.c: In function 'sata_init':
./litex/litex/soc/software/liblitesata/sata.c:87:44:
warning: format '%d' expects argument of type 'int', but
argument 2 has type 'uint32_t' {aka 'long unsigned int'} [-Wformat=]
87 | printf("Capacity: %dGB\n", capacity);
| ~^ ~~~~~~~~
| | |
| int uint32_t {aka long unsigned int}
| %ld
This patch changes `capacity` to `unsigned`, which has the same size
as `uint32_t`, but has the advantage of being treated the same by
`printf` regardless of whether we use the 32- or 64-bit compiler.
2022-06-01 10:52:52 -04:00
a977adf551
build/osfpga: Add workaround to copy .init file to work directory.
2022-05-27 19:39:42 +02:00
c401bdd7f1
Merge pull request #1287 from antmicro/update-zephyr-dts-script
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tools: litex_json2dts_zephyr: Comply with changes in Zephyr
2022-05-26 08:27:13 -07:00
dbe8348288
Add i2s and mmcm handlers
2022-05-26 09:55:14 +02:00
cd5148d961
Update litex_json2dts_zephyr
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Changes in Zephyr require updated script to generate correct overlay.
This commit splits CSR regions that were being added to overlay as
single register into separate registers with names.
It also prints their size in bytes instead of used subregisters.
I also added LITEX_CSR_DATA_WIDTH to generated config parameters.
To limit code duplication, I added functions used for indenting text.
Additionally, I updated formatting functions to take list of registers
and then format it, instead of just surrounding already formatted text
with braces.
2022-05-26 09:54:43 +02:00
0714769926
cores/cpu/cva5: Cleanup/Simplify.
2022-05-25 15:42:31 +02:00
b59a62e51c
cpu/cva6: Add category.
2022-05-25 15:24:30 +02:00
ae89c6bfa4
litex_setup: Only include CVA5 with full install.
2022-05-25 15:20:56 +02:00
888f2d1648
Merge pull request #1300 from e-matthews/cva5
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Add initial CVA5 support
2022-05-25 15:19:51 +02:00
ffcf2fca49
Merge branch 'master' into cva5
2022-05-25 15:18:17 +02:00
3e388a5b58
cores/cpu: Improve address readability with underscores.
2022-05-25 11:40:35 +02:00
e1c132809e
cpu/cva6: Only keep AXI<->AXI-Lite conversion.
2022-05-25 11:28:32 +02:00
808f29ed2e
cpu/cva6/core: Cleanup/Simplify integration.
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- Cosmetic changes and increase similarities with other CPUs.
- Simplification.
- Allow converting AXI to Wishbone or AXI-Lite (Still keep wishbone as default).
- Connect reset from SoC.
- Reorder AXI signals by channels.
- Move JTAG integration to add_jtag method.
2022-05-25 10:20:09 +02:00
69451fad09
test/test_cpu: Disable test_cva6 for now since seems to be failing.
2022-05-25 09:32:30 +02:00
db407b973c
litex_setup: Switch CVA6 to litex-hub and order CPU list per ISA.
2022-05-25 09:29:23 +02:00
73c76c6126
tools/litex_sim: Add pre-definied commented config flags.
2022-05-25 09:17:36 +02:00
7028745829
bios/main: Add CONFIG_BIOS_NO_CRC to disable CRC Check (Useful in simulation).
2022-05-25 09:16:48 +02:00
de6f9e7e83
soc/bios: Cleanup bios manual config flags.
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- CONFIG_WITH_BUILD_TIME -> CONFIG_BIOS_NO_BUILD_TIME.
- CONFIG_SIM_DISABLE_PROMPT -> CONFIG_BIOS_NO_PROMPT.
- CONFIG_DISABLE_DELAYS -> CONFIG_BIOS_NO_DELAYS.
2022-05-25 09:03:45 +02:00
b033d91738
Merge pull request #1294 from suppamax/cva6
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add cva6 cpu
2022-05-24 19:28:57 +02:00
a67cd6e442
build/osfpga: Add include_path support.
2022-05-24 17:33:03 +02:00
3bf5c11928
build/osfpga: Add test_soc.py to test simple SoC builds.
2022-05-24 17:33:00 +02:00
5140668c31
build/osfpga: Rename blinky.py to test_blinky.py.
2022-05-24 17:32:54 +02:00
5bdc0cbc63
build/osfpga: Add macros dict and use it for now to derivate macro from device.
2022-05-24 17:32:49 +02:00
c2e9125d05
Merge pull request #1309 from jevinskie/jev/bug/intel-clocking-indent
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Intel Clocking: compute_config() fix indent causing PLL config error
2022-05-24 09:31:54 +02:00
68fe6a30fd
Intel Clocking: compute_config() fix indent causing PLL config error
2022-05-23 12:12:32 -07:00
6e42082128
Merge pull request #1307 from jevinskie/jev/feat/altera_reset_pretty_names
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AlteraAsyncResetSynchronizer: prettify instance names
2022-05-23 10:00:16 +02:00
90840ff953
Merge pull request #1305 from jevinskie/jev/feat/platform_request_remaining
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Add request_remaining("name") that returns unallocated pins.
2022-05-23 09:57:29 +02:00
b510157b2f
Merge pull request #1304 from jevinskie/jev/bug/quartus-error-bailout
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Quartus build: bail out on error
2022-05-23 09:56:32 +02:00
7d1c9a9001
AlteraAsyncResetSynchronizer: prettify instance names
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This makes debugging e.g. conflicting drivers easier since the errors will display the clock domain name.
2022-05-21 16:22:41 -07:00
0b9ffb6adb
Add request_remaining("name") that returns unallocated pins.
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Improve error reporting on request_all().
2022-05-21 16:03:56 -07:00
9f7028e088
Quartus build: bail out on error
2022-05-21 16:02:25 -07:00
a426ec9e2f
cpu/vexriscv_smp/core: Only use Linux variant (Since similar to standard).
2022-05-20 18:52:46 +02:00
9ee9eb16a4
Merge pull request #1302 from tonymcdowell-rs/master
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litex_setup: fix path reference for python3 binary on non-Linux hosts
2022-05-20 12:12:27 +02:00
2e9b0331db
litex_setup: fix path reference for python3 binary on non-Linux hosts
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the python binary is stored in the "Program Files" directory. without
delimiting the path the calls to the binary will fail on Windows hosts.
2022-05-19 12:50:50 -06:00
c95ddbbff8
UART_POLLING
2022-05-19 15:07:46 +02:00
1d20bbcd01
software/liblitesata/sata_init: Switch to SATA Identify to check if disk is responding and add Identify/Capacity decoding.
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With SATA Disk:
litex> sata_init
Initialize SATA...
Model: KINGSTON SA400S37240G
Capacity: 240GB
Successful.
Without SATA Disk:
litex> sata_init
Initialize SATA... Failed.
2022-05-18 18:01:54 +02:00
04f6b17d03
build: Remove openfpga build backend (Replaced by osfpga build backend).
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OpenFPGA build backend was an experimental build backend for OpenFPGA/SOFA chips.
OpenFPGA is now providing a new FOEDAG build framework abstracting things and providing
a regular .tcl/.sdc based toolchain.
2022-05-18 15:36:30 +02:00
aaf03b3860
soc/add_sata: Integrate LiteSATAIdentify module.
2022-05-18 15:27:13 +02:00
5df1f5f511
soc/add_sata: Add IRQ support.
2022-05-18 15:05:00 +02:00
5c617d139c
Add initial CVA5 support
2022-05-17 20:19:17 -04:00
4401b5a5e8
build/osfpga: Remane FOEDAGToolchain to OSFPGAToolchain and add Foedag/Raptor support through toolchain parameter.
2022-05-17 19:42:26 +02:00
f16f8e5f9e
software/demo/README: Update --build-path (Thanks @mzau).
2022-05-17 19:25:11 +02:00
4810cc15da
soc/LiteXSoCArgumentParser: Fix --cpu-type parsing.
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Could still be improved.
2022-05-17 19:15:06 +02:00
71a5ef2380
build: Add initial OSFPGA/FOEDAG build backend and blinky example.
2022-05-16 16:26:27 +02:00
enjoy-digital
Icenowy Zheng
Gabriel Somlo
Tim 'mithro' Ansell
Michal Sieron
Jevin Sweval
Tony McDowell
Massimiliano Giacometti
Eric Matthews