16 commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	31b1960188	xilinx_ise: add --no-source option to disable sourcing of ISE settings file	2013-04-16 22:39:35 +02:00
Sebastien Bourdeauducq	715d332c3d	crg: apply constraint to IO pins, not internal signals	2013-04-08 20:28:11 +02:00
Sebastien Bourdeauducq	8cf7c96a53	crg: use new platform.request	2013-03-26 23:08:35 +01:00
Sebastien Bourdeauducq	3b19dfc412	Support for platform info	2013-03-26 19:17:35 +01:00
Sebastien Bourdeauducq	003f1950cd	xilinx_ise: fix clock domain names	2013-03-23 19:37:16 +01:00
Sebastien Bourdeauducq	4bf3190244	MultiReg: remove idomain	2013-03-15 19:54:25 +01:00
Sebastien Bourdeauducq	6feb6e60b0	New clock_domain API	2013-03-15 18:46:11 +01:00
Sebastien Bourdeauducq	71c8172836	xilinx_ise/CRG_SE: reset inversion support	2013-03-15 11:31:36 +01:00
Sebastien Bourdeauducq	6a412f796e	xilinx_ise: add lock cycle to bitgen	2013-03-01 11:29:40 +01:00
Sebastien Bourdeauducq	2b902fdcbd	xilinx_ise: import Instance	2013-02-24 15:36:56 +01:00
Sebastien Bourdeauducq	d60ab1d215	Use new 'specials' API	2013-02-24 12:21:01 +01:00
Sebastien Bourdeauducq	56ae0f0714	xilinx_ise: disable SRL extraction on synchronizers	2013-02-23 19:43:12 +01:00
Sebastien Bourdeauducq	f13ad035e1	Support for command line arguments	2013-02-08 22:23:58 +01:00
Sebastien Bourdeauducq	b092237fa6	xilinx_ise: support building files without running ISE	2013-02-08 20:31:45 +01:00
Sebastien Bourdeauducq	7b8e8a19f3	Support adding Verilog/VHDL files	2013-02-08 20:25:20 +01:00
Sebastien Bourdeauducq	fb5130fc1f	Initial version	2013-02-07 22:07:30 +01:00