0006efe6ea
Merge pull request #800 from geertu/doc-sphinx-v1-fix
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doc: Fix doc build with Sphinx v1.x
2021-02-04 12:24:49 +01:00
4d1deffbb0
jtagbone/openocd: add binary mode on JTAGUART to fix "\n" to "\r" remapping that is not wanted in binary mode.
2021-02-04 11:44:43 +01:00
af13f43e60
doc: Fix doc build with Sphinx v1.x
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When building the linux-on-litex-vexriscv documentation with Sphinx
v1.8.5:
Sphinx error:
master file linux-on-litex-vexriscv/build/orangecrab/doc/contents.rst not found
The default value of "master_doc" was changed from "contents" to "index"
in Sphinx v2[1]. As the LiteX doc system creates "index.rst", it thus
fails to build with Sphinx v1.x.
Explicitly configure "master_doc" to "index", to make it work with all
versions of Sphinx, regardless of the default.
[1] https://www.sphinx-doc.org/ca/latest/usage/configuration.html?highlight=master_doc
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-02-04 09:40:04 +01:00
57915db746
build/xilinx: add xc7a200t-sbg484-1 to symbiflow toolchain
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Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-02-03 15:18:48 +01:00
b589959084
Merge pull request #796 from antmicro/jboc/gtkwave-savefiles
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Fix gtkwave.py to be compatible with python 3.6
2021-02-02 16:30:01 +01:00
b1fb141d1f
Fix gtkwave.py to be compatible with python 3.6
2021-02-02 11:14:16 +01:00
ba7c503fb6
tools/litex_sim: move gtkw import to generate_gtkw_savefile.
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This fixes litex_sim use with python 3.6 and raise an error when --gtkwave-savefile
is used with python 3.6.
2021-02-02 10:13:23 +01:00
659751d202
Merge pull request #795 from antmicro/jboc/gtkwave-savefiles
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Add automatic generator of GTKWave savefiles
2021-02-02 09:59:18 +01:00
2f907d6e1e
Merge pull request #790 from antmicro/jboc/8phases
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software/liblitedram: support PHYs with more than 4 DFI phases
2021-02-02 09:43:17 +01:00
d76e0dcede
Merge pull request #791 from antmicro/jboc/init-mr
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software/liblitedram: selectable write leveling MR (for LPDDR4 support)
2021-02-02 09:36:31 +01:00
4c1dbf9991
Merge pull request #794 from geertu/vexriscv-sbt-failures-are-fatal
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cpu/vexriscv_smp: Make sbt failures fatal
2021-02-01 15:16:06 +01:00
7b3737f531
cpu/vexriscv_smp: Make sbt failures fatal
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When using a non-default VexRiscv cluster config, the netlist for that
config needs to be generated. This requires sbt to be installed.
If sbt is missing, an error message is printed:
sh: 1: sbt: not found
This message may easily be lost in the noise, as the build continues, and fails
later with:
ERROR: Can't open input file `litex/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_Ood_Wm.v' for reading: No such file or directory
Make the root cause more visible by raising an OSError, and aborting the
build.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-02-01 13:54:59 +01:00
fc9ef4c255
litex_sim: add --gtkwave-savefile argument with example signals
2021-02-01 13:22:30 +01:00
01b900f4e0
Add GTKWave savefile generator
2021-02-01 13:22:30 +01:00
8623536a8a
build/generic_platform: avoid removing X pins from named_sc.
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We need them on Gowin FPGAs with embedded SDRAM where SDRAM pins are not real IOs.
2021-02-01 13:12:25 +01:00
f324f9531a
build/gowin: Don't generate IO_LOC is pin name is X.
2021-02-01 13:08:37 +01:00
fd33e360fb
Merge pull request #792 from euryecetelecom/master
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Add flash method to openFPGALoader class
2021-01-30 21:35:09 +01:00
14ce5512a2
Merge pull request #793 from d0ntrash/master
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cores/clock/lattice_ice40: add missing AsyncResetSynchronizer import.
2021-01-30 21:34:19 +01:00
3f27253ccc
cores/clock/lattice_ice40: add missing AsyncResetSynchronizer import.
2021-01-30 18:25:19 +01:00
18a5ace637
Add flash method to openFPGALoader class for support with generic_programmer usage (needed for linux-on-litex-vexriscv) + add offset/address support for firmware load
2021-01-30 13:20:30 +01:00
69307cfdde
Merge pull request #789 from antmicro/jboc/litex-sim-fix-name
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litex_sim: fix old name: get_cl_cw -> get_default_cl_cwl
2021-01-29 19:13:34 +01:00
61e605da92
litex_sim: fix old name: get_cl_cw -> get_default_cl_cwl
2021-01-29 11:31:40 +01:00
2287f73937
tools/litex_client: add --read/--write args to do simple MMAP accesses to SoC bus.
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ex reading/writing to scratch register over jtagbone:
In the SoC:
self.add_jtagbone()
Open LiteX Server:
litex_server --jtag
Do the MMAP accesses:
./litex_cli --read 0x4
0x12345678
./litex_clk --write 0x4 0x5aa55aa5
./litex_cli --read 0x4
0x5aa55aa5
2021-01-28 17:46:18 +01:00
38b819c42a
software/liblitedram: selectable write leveling MR (for LPDDR4 support)
2021-01-28 15:56:13 +01:00
e3172faad9
software/liblitedram: support PHYs with more than 4 DFI phases
2021-01-28 15:53:40 +01:00
7abfbd9825
tools/litex_json2dts/ethernet: add missing 'status = "okay";'.
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Was causing https://github.com/litex-hub/linux-on-litex-vexriscv/issues/178 .
2021-01-27 11:52:04 +01:00
b8bcbc522f
integration/export/triple: use LITEX_ENV_CC_TRIPLE instead of TRIPLE.
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triple can be used internally, but is too generic as an environment variable.
2021-01-27 08:25:48 +01:00
f331ddace8
Merge pull request #780 from garytwong/triple-option
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integration/export: allow manually specifying toolchain triple.
2021-01-27 08:16:41 +01:00
61034fe0f9
litex_setup/update: do a git submodule update --init --recursive on repos with recursive set to True.
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Simplify for example pythondata-cpu-vexriscv-smp updates.
2021-01-27 07:55:59 +01:00
2f89e0aecf
soc/do_finalize: check that crg.rst is a Signal before connecting to ctrl._reset.
2021-01-26 17:08:43 +01:00
cafe0944f1
soc/add_uartbone/add_jtagbone: improve phy naming and add uartbone_phy to CSR.
2021-01-26 15:46:55 +01:00
7479cbe71b
Merge pull request #784 from Acathla-fr/patch-1
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Update comm_usb.py
2021-01-26 14:36:07 +01:00
331124dd23
tools/litex_server: add --jtag-config args to provide OpenOCD configuration file.
2021-01-26 14:32:36 +01:00
2e1b9ed948
tools/litex_server: rename --jtag-uart to --jtag.
2021-01-26 14:12:54 +01:00
531ce0e8b7
soc: create specific add_jtagbone method instead of integrating it in add_uartbnone.
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Creates a JTAG bridge in the SoC simply with self.add_jtagbone(), almost comes for free :)
2021-01-26 14:12:19 +01:00
a092d5b28f
Update comm_usb.py
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typo : csr_csr replaced by csr_csv
2021-01-26 12:34:08 +01:00
ed1da7ed1e
soc/add_pcie: expose max_pending_requests parameter.
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Being able to configure it is useful to find resource usage/performance compromise.
2021-01-26 10:59:22 +01:00
dd985cd1d0
integration/export: disable CSRField extract/read functions generation for csr.size > 32-bit.
2021-01-26 10:23:56 +01:00
2a542e150d
jtag_uart/openocd: switch to raw tcp socket and get litex_server --jtag-uart working.
2021-01-25 16:33:43 +01:00
7799765471
soc/jtag: run JTAGPHY in sys_jtag clock domain (to fix behavior after reset).
2021-01-25 16:31:55 +01:00
213644af70
integration/soc/add_uart: ResetInserter no longer required on UART since reboot is now doing a full system reset.
2021-01-25 13:39:45 +01:00
8cada67f32
cores/jtag: cleanup instances.
2021-01-25 12:31:32 +01:00
0b5df58a1b
cores/jtag: cores/uart: expose jtag/tx/rx_cdc (to ease probing with LiteScope).
2021-01-25 12:30:43 +01:00
4df336341b
cores/uart: expose fsm/timer (to ease probing with LiteScope).
2021-01-25 12:29:18 +01:00
17195c5e96
cpu/vexriscv_smp: cleanup new args integration and fix cluster naming.
2021-01-25 11:48:05 +01:00
7fa03cb1f3
Merge pull request #782 from enjoy-digital/vexriscv-smp-no-litedram
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soc/cpu/vexriscv-smp: add args to disable out of order or direct path to LiteDRAM
2021-01-25 08:45:03 +01:00
1a38d51e08
libbase/memtest: remove 0x no longer required with %p.
2021-01-24 21:09:19 +01:00
ae2cd31573
soc/cpu/vexriscv-smp add --without-out-of-order-decode and --with-wishbone-memory
2021-01-23 20:38:50 +01:00
01a2fc11e2
integration/soc/usb_acm: run USB ACM in sys_usb clock domain similar to sys clock domain but with rst disconnected.
2021-01-22 22:57:24 +01:00
13d1d4cf8e
integration/export: allow manually specifying toolchain triple.
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If the environment variable TRIPLE is defined, use its value as the
highest priority candidate. Useful for testing new cross-compilers,
or selecting among toolchains in a different priority than the built-in
list.
2021-01-22 12:11:03 -07:00
enjoy-digital
Geert Uytterhoeven
Jan Kowalewski
Jędrzej Boczar
Konstantin
Guillaume REMBERT
Acathla-fr
Dolu1990
Gary Wong