07e0153bb1
CHANGES: update.
2020-05-04 09:59:01 +02:00
2112703181
cpu/microwatt: add powerpc64le-linux-gnu to gcc_triple.
...
It seems to be what most distros cross-comiplers are using.
2020-05-04 08:51:38 +02:00
c06a127909
cpu/microwatt: add pythondata and fix build with it.
2020-05-04 08:46:25 +02:00
45377d9faa
cpus: use a common definition of gcc_triple for the RISC-V CPUs, reorganize CPU by ISA/Data-Width.
2020-05-03 21:29:54 +02:00
7c69a6dbba
bios/cmd_mdio.c: fix missing <base/mdio.h> import.
2020-05-03 10:54:35 +02:00
b02053357c
cpu/vexriscv: fix flush_cpu_icache, remove workaround on boot.c.
2020-05-02 20:07:52 +02:00
97e534d0b6
cpus: add nop instruction and use it to simplify the BIOS.
2020-05-02 12:52:25 +02:00
4efc783534
cpus: add human_name attribute and use it to simplify the BIOS.
2020-05-02 11:52:58 +02:00
d81f171c8a
software/libbase/system.c: remove unused includes.
2020-05-02 11:27:22 +02:00
3bbadb35bf
Merge pull request #492 from scanakci/blackparrot_litex
...
BP -> Linux simulation, Comply with pythondata, and README update
2020-05-02 11:25:34 +02:00
999b93af0a
Merge branch 'master' into blackparrot_litex
2020-05-02 11:16:33 +02:00
705d388745
Merge pull request #474 from fjullien/term_hist_auto_compl
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Terminal: add history and auto completion
2020-05-02 10:45:12 +02:00
0c770e0683
Update README.md
2020-05-02 02:51:41 -04:00
19bb1b9b8c
update to comply with python-data layout
2020-05-01 23:44:20 -04:00
3eb9efd64f
BP fpga recent version
2020-05-01 16:27:30 -04:00
bf864d335b
Fix memory transducer bug, --with-sdram for BIOS works, memspeed works
2020-05-01 16:27:27 -04:00
cf01ea65f3
rebased, minor changes in core.py
2020-05-01 16:25:01 -04:00
b7b9a1f0fb
Linux works, LiteDRAM works (need cleaning, temporary push)
2020-05-01 16:24:58 -04:00
74140587c8
Create GETTING STARTED
...
Rename GETTING STARTED to GETTING STARTED.md
Update GETTING STARTED.md
Update GETTING STARTED.md
Update GETTING STARTED.md
2020-05-01 16:20:35 -04:00
e853cac6b6
Merge pull request #483 from ilya-epifanov/lattice-openocd-jtag-programmer-erase-flag-and-quiet-output
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Lattice OpenOCD JTAG programmer: removed erase flag and made progress output less noisy
2020-05-01 21:18:09 +02:00
a6779b9d61
Merge pull request #491 from gsomlo/gls-spisd-clusters
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software: spisdcard: cosmetic: avoid filling screen with cluster numbers
2020-05-01 21:17:38 +02:00
b5978b214d
.travis.yml: disable python3.5 test (nMigen requires 3.6+).
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As discussed in #479 .
2020-05-01 21:14:17 +02:00
10371a33f9
CHANGES: update.
2020-05-01 20:13:05 +02:00
bd8a410047
cpu/minerva: add pythondata and use it to compile the sources.
2020-05-01 20:12:02 +02:00
e4a4659d4d
litex_setup: add nmigen dependency (used to generate Minerva CPU).
...
This also requires Yosys, but Yosys is already expected to be installed separately.
2020-05-01 19:10:13 +02:00
d3e3ca0618
CHANGES: start listing changes for next release.
2020-05-01 19:07:43 +02:00
c8e3bba4b7
software: spisdcard: cosmetic: avoid filling screen with cluster numbers
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-01 09:49:16 -04:00
3c70c83f9b
cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs.
2020-05-01 12:41:14 +02:00
74dc444b02
bios: add auto completion for commands
2020-05-01 12:12:35 +02:00
fc2b8226c5
bios: switch command handler to a modular format
...
Command are now described with a structure. A pointer to this
structure is placed in a dedicated linker section.
2020-05-01 12:12:35 +02:00
86cab3d362
bios: move helper functions to their own file
2020-05-01 12:12:35 +02:00
bc5a1986e2
bios: add terminal history
...
Terminal history and characters parsing is done in readline.c.
Passing TERM_NO_HIST disable terminal history.
Passing TERM_MINI use a simple terminal implementation in order to save
more space.
2020-05-01 12:12:07 +02:00
e764eabda1
builder: add a parameter to pass options to BIOS Makefile
2020-05-01 12:10:50 +02:00
bb70a2325a
cpu/software: move CPU specific software from the BIOS to the CPU directories.
...
This simplifies the integration of the CPUs' software, avoid complex switches in the code,
and is a first step to make CPUs fully pluggable.
The CPU name is no longer present in the crt0 files (for example crt0-vexriscv-ctr.o
becomes crt0-ctr.o) so users building firmwares externally will have to update their
Makefiles to remove the $(CPU) from crt0-$(CPU)-ctr.o.
2020-05-01 11:04:54 +02:00
0abc7d4f0b
cpu/Minerva: Clone the repository locally for now, we need to create a pythondata repository.
2020-05-01 11:03:07 +02:00
b82b3b7ecf
integration/soc: rename usb_cdc to usb_acm.
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As discussed on Discord recently.
2020-04-30 21:45:53 +02:00
0a1afbf66f
litex/__init__.py: remove retro-compat > 6 months old.
2020-04-30 21:31:58 +02:00
3531a64173
soc: allow passing custom CPU class to SoC.
...
Useful to experiment with custom CPU wrappers and a first step to make CPUs plugable.
2020-04-29 20:12:23 +02:00
64b505156e
Add RDIMM side-B inversion support
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:28:53 +01:00
90a6343df1
Merge pull request #488 from enjoy-digital/python3.5
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travis: add back test on python3.5 (python3.6 is recommended but we c…
2020-04-29 08:48:06 +02:00
9941e4c16b
travis: add back test on python3.5 (python3.6 is recommended but we can try to keep 3.5 compatibility until we have good reason to no longer support it).
2020-04-29 08:43:02 +02:00
83f4dcb2c6
Added `imac` config for CPUs which implements the most basic working riscv32imac feature set, implemented for VexRiscv
2020-04-28 22:27:35 +02:00
ac1e968351
Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs`
2020-04-28 22:25:57 +02:00
a11f1c39b7
Removed erase flag and made progress output less noisy
2020-04-28 22:22:33 +02:00
855d614e5d
Merge pull request #481 from betrusted-io/unfstringify
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propose patch to not break litex for python 3.5
2020-04-28 19:05:08 +02:00
17b766546b
propose patch to not break litex for python 3.5
2020-04-29 00:34:19 +08:00
00f973ea35
spi_flash: extend non-bitbanged flash support
...
This commit adds support for memory mapped writes
in the same configuration as memory mapped reads
are currently supported.
It also adds support for accessing registers
and erasing sectors in non-bitbanged single SPI
mode.
2020-04-28 15:02:55 +02:00
56aa7897df
create first release, add CHANGES and note about Python modules in README.
2020-04-28 11:36:44 +02:00
6d0896de1d
cpu/serv: switch to pythondata package instead of local git clone.
2020-04-28 10:34:39 +02:00
1b06926882
README: update Python minimal version to 3.6.
2020-04-28 09:02:59 +02:00
Florent Kermarrec
Sadullah Canakci
Gabriel Somlo
Franck Jullien
David Shah
Ilya Epifanov
bunnie
Jakub Cebulski