Commit Graph

3893 Commits

Author SHA1 Message Date
Florent Kermarrec 3b27d2ae89 soc/integration/cpu_interface: generate error if unable to find any of the cross compilation toolchains 2018-10-06 21:32:38 +02:00
Florent Kermarrec 168b07b9a2 soc_core: add csr range check 2018-10-06 20:55:16 +02:00
enjoy-digital 6febb6826c
Merge pull request #112 from cr1901/8k-b-evn
build/platforms: Add ice40_hx8k_b_evn from Migen.
2018-10-04 21:12:33 +02:00
enjoy-digital 9cf4ffb3f4
Merge pull request #113 from stffrdhrn/litex-trivial
Litex trivial
2018-10-04 16:25:11 +02:00
Stafford Horne ff6de429f0 Fix help for or1k builds
The help said cpu-type could be mor1kx, which is correct but you must
pass or1k to get mor1kx.  Fix the message to properly represent what
needs to be passed to the commandline.
2018-10-04 23:09:49 +09:00
Stafford Horne dafdb8df72 Fix compiler warnings from GCC 8.1
Fix these 2 warnings:

 litex/build/sim/core/libdylib.c:42:5: warning: 'strncpy' specified bound 2048 equals destination size
 [-Wstringop-truncation]
     strncpy(last_err, s, ERR_MAX_SIZE);
     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 In function 'set_last_error',

 litex/soc/software/libbase/exception.c:28:13: warning: function declaration isn't a prototype [-Wstrict-prototypes]
  static char emerg_getc()
2018-10-04 23:07:48 +09:00
Florent Kermarrec 2be5205463 build/xilinx/common: update XilinxDDRInputImplS7 and XilinxDDRInputImplKU (from migen) 2018-10-04 08:17:44 +02:00
William D. Jones 9a44f08a3e build/platforms: Add ice40_hx8k_b_evn from Migen. 2018-10-03 20:53:33 -04:00
Florent Kermarrec 948527b0fe cores/cpu: revert vexriscv (it seems there is a regression in last version) 2018-10-02 12:30:11 +02:00
Florent Kermarrec 15bca4535f targets/sim: fix integrated_main_ram_size when with_sdram 2018-10-02 11:31:08 +02:00
Florent Kermarrec 6e327cda26 bios/sdram: rewrite write_leveling (simplify and improve robustness) 2018-10-01 15:38:19 +02:00
Florent Kermarrec 975be6686f platforms/genesys2: add eth clock timing constraint 2018-10-01 15:37:34 +02:00
Florent Kermarrec 934a5da559 soc/cores/clock: add expose_drp on S7PLL/S7MMCM 2018-09-28 13:02:10 +02:00
enjoy-digital 9097573e71
Merge pull request #109 from cr1901/xip-improve
Improve XIP Support
2018-09-25 15:32:04 +02:00
Florent Kermarrec 082b03016c targets: use new clock abstraction on all 7-series targets 2018-09-25 09:31:30 +02:00
Florent Kermarrec 74e74dc0e7 soc/cores/clock: different clkin_freq_range for pll and mmcm 2018-09-25 09:09:47 +02:00
Florent Kermarrec 91d8cc2d6a soc/cores/clock: different vco_freq_range for pll and mmcm 2018-09-25 09:04:38 +02:00
Florent Kermarrec 6cd954940c soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG) 2018-09-25 08:36:18 +02:00
Florent Kermarrec 912ca3236b soc/cores/clock: create specific S7IDELAYCTRL module 2018-09-24 23:22:59 +02:00
Florent Kermarrec baec87f530 soc/cores/clock: add S7MMCM support 2018-09-24 23:20:12 +02:00
Florent Kermarrec ef40524924 soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest) 2018-09-24 22:58:23 +02:00
Florent Kermarrec 5415b521be targets/arty: use new clock abstraction module (compile, untested on board) 2018-09-24 22:49:30 +02:00
Florent Kermarrec 63fc395006 soc/cores: init clock abstraction module 2018-09-24 22:49:01 +02:00
William D. Jones 0ff6d58605 Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section). 2018-09-24 14:48:54 -04:00
William D. Jones 8106008184 integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM. 2018-09-24 12:28:45 -04:00
William D. Jones db90619067 integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX). 2018-09-24 11:04:57 -04:00
Florent Kermarrec 70a32ed86f sim/verilator: add multithread support (default=1) 2018-09-24 12:43:29 +02:00
Florent Kermarrec 7f0d116d88 soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now) 2018-09-24 10:59:32 +02:00
Florent Kermarrec 22febe9582 boards/targets: uniformize things between targets 2018-09-24 10:58:10 +02:00
Florent Kermarrec 01b025aafd soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication 2018-09-24 08:01:32 +02:00
Florent Kermarrec b528a005a0 cores/cpu: add software informations to cpu and simplify cpu_interface 2018-09-24 07:51:41 +02:00
Florent Kermarrec 2d785cb0ac boards/plarforms: fix issues found while testing simple design on all platforms 2018-09-24 02:03:30 +02:00
Florent Kermarrec 0b0e3ac1dd test/test_targets: test simple design with all platforms 2018-09-24 02:02:14 +02:00
Florent Kermarrec c88029d330 soc_core: add uart-stub argument 2018-09-24 02:01:15 +02:00
Florent Kermarrec 0d2d3959f1 setup.py: add litex_simple exec (to ease building simple design) 2018-09-24 01:24:51 +02:00
Florent Kermarrec e04530e0c4 test/test_targets: update and reorganize targets 2018-09-24 01:15:33 +02:00
Florent Kermarrec e9ed737037 ease RemoteClient import 2018-09-23 10:23:00 +02:00
enjoy-digital 346dcf94dc
Merge pull request #108 from xobs/use-csr-accessors
Use csr accessors when generating `csr.h`
2018-09-23 09:59:37 +02:00
Sean Cross 6f25a0d8a1 csr: use external csr_readl()/csr_writel() if present
If the variable CSR_ACCESSORS_DEFINED is set, then use external
csr_readl() and csr_writel() instead of locally-generated inline
functions.

With this patch, csr.h can be used with etherbone.h and litex_server to
prototype drivers remotely.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-09-22 16:55:09 +02:00
Sean Cross 9a252e367c csr: use readl()/writel() accessors for accessing mmio
Instead of directly dereferencing pointers, use variants on readl()/writel().
This way we can replace these functions with others for remote access
when writing drivers and code outside of the litex environment.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-09-22 16:54:46 +02:00
Tim Ansell 1c1d87f845
Merge pull request #106 from cr1901/data-crt0
libbase/crt0-lm32.S: Add provisions for loading .data from flash.
2018-09-22 15:21:35 +01:00
William D. Jones 9d4da737ff libbase/crt0-lm32.S: Add provisions for loading .data from flash.
:100644 100644 e0cd7153 34428845 M	litex/soc/software/libbase/crt0-lm32.S
2018-09-21 10:23:14 -04:00
Florent Kermarrec 01ae7d4235 README: add migen/litex clarification 2018-09-21 07:37:31 +02:00
Florent Kermarrec 15e584d880 targets/sim: generate analyzer.csv 2018-09-20 12:20:48 +02:00
Florent Kermarrec cde72603a1 targets/sim: generate csr.csv 2018-09-20 11:17:18 +02:00
Florent Kermarrec f62df5023f targets/sim: add rom-init 2018-09-20 01:14:00 +02:00
Florent Kermarrec 1dbf591e78 targets/sim: add ram-init param to allow initializing ram from file (faster than tftp) 2018-09-20 01:00:13 +02:00
Florent Kermarrec 9893c2460a integration/soc_core: add get_mem_data function to read memory content from file 2018-09-20 00:46:06 +02:00
Florent Kermarrec a3eb2e403b soc/intergration/builder: fix when no sdram 2018-09-19 23:59:42 +02:00
Florent Kermarrec 934b08ede8 targets/sim: merge in a single class and ease configuration 2018-09-19 23:59:15 +02:00