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6442 Commits

Author SHA1 Message Date
Dave Marples 967e38bb57 Small fixups to address compiler warnings etc. 2020-05-07 09:26:46 +01:00
Florent Kermarrec 84841e1d58 bios/sdram: fix merge typo in lfsr (thanks Benjamin Herrenschmidt). 2020-05-07 08:21:57 +02:00
Benjamin Herrenschmidt 99c5b0fca1 bios/sdram: Use an LFSR to speed up pseudo-random number generation 
This speeds up the memory test by an order of magnitude, esp. on
cores without a hardware multiplier by getting rid of the
multiplication in the loop.

The LFSR implementation comes from microwatt's simple_random test
project.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-05-06 21:56:10 +02:00
enjoy-digital 34f268689a
Merge pull request #499 from DurandA/patch-2 
Add data dirs to manifest
 2020-05-06 18:54:23 +02:00
Florent Kermarrec 8b9aa16d2e boards/platforms: update xilinx programmers. 2020-05-06 16:16:41 +02:00
Florent Kermarrec 3c34039b73 build/xilinx/vivado: ensure Vivado process our .xdc early. 
When generating the LitePCIe PHY wrappers from the .xci, Vivado is locking the
PCIe lanes to default locations that do not necessarily match the ones used in
the design.

Processing our constraints earlier makes Vivado use our constraints and not the
ones from the generated wrapper.
 2020-05-06 13:13:01 +02:00
Arnaud Durand 5e049d8966 Add data dirs to manifest 2020-05-05 22:15:24 +02:00
Florent Kermarrec b057858071 gen/fhdl/verilog: explicitly define input/output/inout wires. 
When integrating designs which set `default_nettype none, the top also needs
to explicitly define the type of the signals.
 2020-05-05 16:58:33 +02:00
Florent Kermarrec 0aa3c339cc targets/genesys2: set cmd_latency to 1. 2020-05-05 16:33:14 +02:00
Florent Kermarrec 95b57899cd bios: remove usddrphy debug (we'll use a specific debug firmware to fix the usddrphy corner cases). 2020-05-05 16:27:21 +02:00
Florent Kermarrec 98d1b45157 platforms/targets: fix CI. 2020-05-05 15:55:09 +02:00
Florent Kermarrec 22bcbec03a boards: keep in sync with LiteX-Boards, integrate improvements. 
- create_programmer on all platforms.
- input clocks automatically constrainted.
- build/load parameters.
 2020-05-05 15:27:56 +02:00
Florent Kermarrec 28f85c7403 build/lattice/programmer: add UJProg (for ULX3S). 2020-05-05 13:31:58 +02:00
Florent Kermarrec 85ac5ef133 build/lattice/programmer: make OpenOCDJTAGProgrammer closer to OpenOCD programmer. 2020-05-05 12:17:12 +02:00
Florent Kermarrec 9a7f9cb87b build/generic_programmer: catch 404 not found when downloading config/proxy. 2020-05-05 12:16:29 +02:00
Florent Kermarrec d0b8daa005 build/platform: allow doing a loose lookup_request (return None instead of ConstraintError) and allow subname in lookup_request. 
In the platforms, insead of doing:
self.lookup_request("eth_clocks").rx
we can now do:
self.lookup_request("eth_clocks:rx")

This allows some try/except simplifications on constraints.
 2020-05-05 11:23:46 +02:00
Florent Kermarrec b8f9f83a8f build/openocd: add find_config method to allow using local config file or download it if not available locally. 2020-05-05 09:56:13 +02:00
Florent Kermarrec 9bef218ad6 cpu/microwatt: fix integration/crt0.S (thanks Benjamin Herrenschmidt). 
Tested on Arty A7:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on May  4 2020 17:15:13
 BIOS CRC passed (0adc4193)

 Migen git sha1: 5b5e4fd
 LiteX git sha1: 6f24d46d

--=============== SoC ==================--
CPU:       Microwatt @ 100MHz
ROM:       32KB
SRAM:      4KB
L2:        8KB
MAIN-RAM:  262144KB

--========== Initialization ============--
Initializing SDRAM...
SDRAM now under software control
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |00000000000000000000000000000000| delays: -
m0, b5: |00000000000000000000000000000000| delays: -
m0, b6: |00000111111111111100000000000000| delays: 11+-06
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b6 delays: 11+-06
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |00000000000000000000000000000000| delays: -
m1, b5: |10000000000000000000000000000000| delays: 00+-00
m1, b6: |00000011111111111100000000000000| delays: 12+-06
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b6 delays: 12+-06
SDRAM now under hardware control
Memtest OK
Memspeed Writes: 129Mbps Reads: 215Mbps

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2020-05-04 17:30:50 +02:00
enjoy-digital 6f24d46dbd
Merge pull request #496 from gsomlo/gls-fix-makefiles 
software/*/Makefile: no need to copy .S files from CPU directory
 2020-05-04 15:29:05 +02:00
Gabriel Somlo edfed4f068 software/*/Makefile: no need to copy .S files from CPU directory 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-05-04 09:16:52 -04:00
enjoy-digital 7f8e34c65d
Merge pull request #494 from shuffle2/patch-2 
diamond: quiet warning about missing clkin freq for EHXPLLL
 2020-05-04 11:53:10 +02:00
shuffle2 ee413527ac
diamond: quiet warning about missing clkin freq for EHXPLLL 
FREQUENCY_PIN_CLKI should be given in mhz
 2020-05-04 01:10:09 -07:00
Florent Kermarrec 07e0153bb1 CHANGES: update. 2020-05-04 09:59:01 +02:00
Florent Kermarrec 2112703181 cpu/microwatt: add powerpc64le-linux-gnu to gcc_triple. 
It seems to be what most distros cross-comiplers are using.
 2020-05-04 08:51:38 +02:00
Florent Kermarrec c06a127909 cpu/microwatt: add pythondata and fix build with it. 2020-05-04 08:46:25 +02:00
Florent Kermarrec 45377d9faa cpus: use a common definition of gcc_triple for the RISC-V CPUs, reorganize CPU by ISA/Data-Width. 2020-05-03 21:29:54 +02:00
Florent Kermarrec 7c69a6dbba bios/cmd_mdio.c: fix missing <base/mdio.h> import. 2020-05-03 10:54:35 +02:00
Florent Kermarrec b02053357c cpu/vexriscv: fix flush_cpu_icache, remove workaround on boot.c. 2020-05-02 20:07:52 +02:00
Florent Kermarrec 97e534d0b6 cpus: add nop instruction and use it to simplify the BIOS. 2020-05-02 12:52:25 +02:00
Florent Kermarrec 4efc783534 cpus: add human_name attribute and use it to simplify the BIOS. 2020-05-02 11:52:58 +02:00
Florent Kermarrec d81f171c8a software/libbase/system.c: remove unused includes. 2020-05-02 11:27:22 +02:00
enjoy-digital 3bbadb35bf
Merge pull request #492 from scanakci/blackparrot_litex 
BP -> Linux simulation, Comply with pythondata, and README update
 2020-05-02 11:25:34 +02:00
enjoy-digital 999b93af0a
Merge branch 'master' into blackparrot_litex 2020-05-02 11:16:33 +02:00
enjoy-digital 705d388745
Merge pull request #474 from fjullien/term_hist_auto_compl 
Terminal: add history and auto completion
 2020-05-02 10:45:12 +02:00
Sadullah Canakci 0c770e0683 Update README.md 2020-05-02 02:51:41 -04:00
sadullah 19bb1b9b8c update to comply with python-data layout 2020-05-01 23:44:20 -04:00
sadullah 3eb9efd64f BP fpga recent version 2020-05-01 16:27:30 -04:00
sadullah bf864d335b Fix memory transducer bug, --with-sdram for BIOS works, memspeed works 2020-05-01 16:27:27 -04:00
sadullah cf01ea65f3 rebased, minor changes in core.py 2020-05-01 16:25:01 -04:00
sadullah b7b9a1f0fb Linux works, LiteDRAM works (need cleaning, temporary push) 2020-05-01 16:24:58 -04:00
Sadullah Canakci 74140587c8 Create GETTING STARTED 
Rename GETTING STARTED to GETTING STARTED.md

Update GETTING STARTED.md

Update GETTING STARTED.md

Update GETTING STARTED.md
 2020-05-01 16:20:35 -04:00
enjoy-digital e853cac6b6
Merge pull request #483 from ilya-epifanov/lattice-openocd-jtag-programmer-erase-flag-and-quiet-output 
Lattice OpenOCD JTAG programmer: removed erase flag and made progress output less noisy
 2020-05-01 21:18:09 +02:00
enjoy-digital a6779b9d61
Merge pull request #491 from gsomlo/gls-spisd-clusters 
software: spisdcard: cosmetic: avoid filling screen with cluster numbers
 2020-05-01 21:17:38 +02:00
Florent Kermarrec b5978b214d .travis.yml: disable python3.5 test (nMigen requires 3.6+). 
As discussed in #479.
 2020-05-01 21:14:17 +02:00
Florent Kermarrec 10371a33f9 CHANGES: update. 2020-05-01 20:13:05 +02:00
Florent Kermarrec bd8a410047 cpu/minerva: add pythondata and use it to compile the sources. 2020-05-01 20:12:02 +02:00
Florent Kermarrec e4a4659d4d litex_setup: add nmigen dependency (used to generate Minerva CPU). 
This also requires Yosys, but Yosys is already expected to be installed separately.
 2020-05-01 19:10:13 +02:00
Florent Kermarrec d3e3ca0618 CHANGES: start listing changes for next release. 2020-05-01 19:07:43 +02:00
Gabriel Somlo c8e3bba4b7 software: spisdcard: cosmetic: avoid filling screen with cluster numbers 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-05-01 09:49:16 -04:00
Florent Kermarrec 3c70c83f9b cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs. 2020-05-01 12:41:14 +02:00