bc68351475
software/liblitedram: use SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE flag.
2020-10-12 16:05:44 +02:00
c596135274
bios/cmd/cmd_litedram: add sdram_test command.
2020-10-12 13:52:15 +02:00
d4d4ca53b0
software/liblitedram/sdram.c: move activate/precharge to sdram_write_read_check_test_pattern, change second seed.
2020-10-12 13:00:44 +02:00
d1f04e67c5
software/liblitedram: use 2 cycles increment on write bitslip (for tCK steps).
2020-10-12 10:58:43 +02:00
3d5bc29dd1
software/liblitedram: add initial write latency calibration.
2020-10-09 20:04:16 +02:00
3518223c84
software/liblitedram: add functions to simplify read_leveling and do the test with 2 seeds.
...
Doing the test with 2 seeds prevents the test to success if previous content in DRAM was
still the expected one (ex after a sdram_cal command that succeded).
2020-10-09 15:50:44 +02:00
69177c9251
software/liblitesdram: add initial support for write leveling bitslip (configurable via bios commands).
2020-10-08 19:38:57 +02:00
004924a319
soc/interconnect/csr: expose re on CSRStatus (to allow triggering actions on CSRStatus writes).
2020-10-08 11:34:57 +02:00
b904aa7d18
libbase/memtest: simplify logs and add test size to memtest/memspeed banner.
2020-10-08 09:11:28 +02:00
e4fe0d9ef4
soc/cores/spi_flash: fix with_bitbang=False compilation.
2020-10-07 19:32:10 +02:00
375b6f2dc7
soc/cores/spi_flash: fix Dual mode compilation.
2020-10-07 19:28:13 +02:00
a2b71fde4a
soc: change default CSR bus data-width to 32.
...
A CSR bus data-width of 32 has been validated on very various design and is
now recommended. It provides better performance without impacting resource
usage (even on iCE40).
2020-10-07 16:38:49 +02:00
4f30a5b8e5
libbase/memtest: add memtest_data_speed function that prints speed in B/KiB/MiB/GiB/s depending the value.
2020-10-07 13:01:14 +02:00
0a80e4c3d6
libbase/memtest: revert previous printf (the informations are provided below and this make it too verbose).
2020-10-07 12:42:58 +02:00
5e2a4efac6
Merge pull request #665 from fidergo-stephane-gourichon/more_precise_log
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More precise memory performance test.
2020-10-07 12:38:44 +02:00
83b4447f0e
Merge pull request #662 from fidergo-stephane-gourichon/dfu-util_with_-R
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Unconditionally ask dfu-util to "Issue USB Reset"
2020-10-07 12:37:53 +02:00
305092c7b8
test/test_icap: update.
2020-10-07 12:36:08 +02:00
ad7671f811
soc/cores/icap/ICAP: add with_csr parameter and add_reload method to allow reloading the FPGA from the logic.
2020-10-06 17:38:39 +02:00
42025dcbfa
Merge pull request #666 from gsomlo/gls-sdcard-cd
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bios: add command returning card-detect pin status
2020-10-06 10:31:25 +02:00
026d40ffab
bios: add command returning card-detect pin status
2020-10-05 14:32:06 -04:00
6916674ff6
Merge pull request #664 from antmicro/symbiflow_a100T
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build/xilinx/symbiflow: Add xc7a100tscg324-1 to supported devices
2020-10-05 19:25:18 +02:00
81257da9b4
Merge pull request #663 from fidergo-stephane-gourichon/fix_crash_on_minimal_cpu
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Fix SoC CPU crash on minimal variants on call to flush_cpu_dcache().
2020-10-05 19:24:43 +02:00
1a603b3fee
Merge pull request #654 from pepijndevos/gowin
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Build support for Gowin
2020-10-05 19:23:47 +02:00
f71275a3f1
Show speeds in bytes per second.
...
Forcing megabytes per second for everyone does not make sense.
Showing bytes per second allows to distinguish between low performance and a performance measurement bug.
Anyway previous code claims speeds were in MiB/s, they were not, actually MB/s.
2020-10-05 18:46:05 +02:00
cbbbb3f468
Only display write speed if write test actually performed.
2020-10-05 18:43:45 +02:00
5b0ced00b5
Confirm parameters in log.
2020-10-05 17:58:44 +02:00
48638f936b
Fix SoC CPU crash on minimal variants on call to flush_cpu_dcache().
...
Generated soc.h says for example
but code tester for CONFIG_CPU_VARIANT_MIN not MINIMAL.
Attempted to run instruction unknown to this CPU, most likely cause of hang.
2020-10-05 17:16:35 +02:00
e47f84ea79
Unconditionally ask dfu-util to "Issue USB Reset signalling once we're finished".
...
Some host machines need it.
If issuing -R always does not cause any trouble, then do it.
2020-10-05 17:16:10 +02:00
aebe08d841
Merge pull request #661 from yetifrisstlama/fix_stream2wishbone
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Fix stream2wishbone
2020-10-05 17:16:04 +02:00
2d6f19a816
Merge pull request #659 from shawnanastasio/toolchain-fixes
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Add riscv*-unknown-linux-gnu triples and fix existing riscv-linux-gnu triple
2020-10-05 17:09:59 +02:00
ff4afda305
build/xilinx/symbiflow: Add xc7a100tscg324-1 to supported devices
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Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
2020-10-05 17:02:51 +02:00
acdfae202b
Stream2Wishbone: drive sink.ready line
2020-10-04 18:19:39 -07:00
6e3e979a0b
serial2tcp.c json error handling, respect rx.ready
2020-10-04 18:17:28 -07:00
fa82d97aa5
cores/cpu: Add riscv*-unknown-linux-gnu triple, fix riscv-linux-gnu
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Add riscv*-unknown-linux-gnu to known triples, and fix the existing
riscv-linux-gnu by removing the incorrect -gcc suffix from the
triple.
2020-10-02 18:31:48 -05:00
6fd48ca2ce
software: Use -fno-stack-protector
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This allows riscv*-gnu-linux toolchains to be used to build LiteX
software. Without this, references to undefined stack guard symbols
get generated and linking fails.
2020-10-02 13:42:16 -05:00
c77da3a8bc
RFC: json2dts: set CPU clock-frequency and SoC bus-frequency
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FIXME: timebase-frequency isn't to be used as the raw CPU clock, so
on vexriscv we might want to re-evaluate also setting *that* to the
`CONFIG_CLOCK_FREQUENCY`. Decide whether to keep the SoC's
`bus-frequency` cell, or whether to go with the CPU's `clock-frequency`
only.
2020-10-01 06:59:45 -04:00
b84a858b2c
CHANGES: initialize changes since last release.
2020-10-01 11:46:43 +02:00
ba2ff8cf71
tools/litex_sim: update get_sdram_phy_settings (rd/wrcmdphase no longer exposed as PhySettings).
2020-10-01 11:27:33 +02:00
2b62802961
tools/litex_sim: minor review cleanup.
2020-10-01 10:36:37 +02:00
23e319732c
tools/litex_server: minor review cleanup.
2020-10-01 10:35:11 +02:00
e8c0360fa5
tools/{litex_sim, litex_server}.py: Minor clean-up ( #657 )
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Enable litex_server debug and create function to add for litex_sim args.
2020-10-01 10:32:44 +02:00
890ccaf4bd
support writing bitstream to flash
2020-10-01 08:39:32 +02:00
29bff18e69
software/liblitedram: add SDRAM CL/CWL printf to BIOS.
2020-09-30 19:00:12 +02:00
f476b32ada
software/liblitedram: rename SDRAM_TEST_SIZE to MEMTEST_DATA_SIZE (since used in benchs to force test size).
2020-09-30 18:34:48 +02:00
f7e49cc23a
software/liblitedram: add SDRAM_TEST_SIZE (2MiB as previously defined in memtest).
2020-09-30 18:02:07 +02:00
fdf7981f40
software/libbase/memtest: remove size restriction and don't execute memspeed.
2020-09-30 17:49:51 +02:00
ed21c983cb
Merge branch 'master' of http://github.com/enjoy-digital/litex
2020-09-30 17:29:04 +02:00
c154f1cbb2
software/liblitedram: add support for dynamic read/write phase and add command to BIOS to force them.
2020-09-30 17:09:19 +02:00
6f136f9faa
Merge pull request #655 from betrusted-io/svd_memregion
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add memory regions to soc.svd
2020-09-30 11:43:14 +02:00
96976941b4
Merge pull request #656 from kbeckmann/fix_sdram_leveling
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Fix build issue where sdram_leveling is not found
2020-09-30 09:57:54 +02:00
Florent Kermarrec
Gabriel Somlo
Stephane Gourichon
Robert Winkler
Michael Betz
Shawn Anastasio
Vamsi Vytla
Pepijn de Vos