8d1c555e36
misoclib/com/uart: remove irq condition parameters and use "non-full" for tx irq, "non-empty" for rx irq.
...
An optimal solution for both sync and async mode is not easy to implement, it would requires moving CDC out of UART module and handling in the PHY with AsyncFIFO or minimal depth.
For now use the solution that works for both cases. We'll try to optimize that if we have performance issues.
2015-07-25 00:25:09 +02:00
b75b93df43
misoclib/com/uart: replace revered Migen FIFO function with specific _get_uart_fifo function for our use case.
2015-07-24 14:05:54 +02:00
d73d75007e
misoclib/com/uart: cleanup and add irq condition parameters
...
- reintroduce RX/TX split (ease comprehension)
- use FIFO wrapper function from Migen.
- add tx_irq_condition and rx_irq_condition
2015-07-24 12:57:42 +02:00
a501d7c52d
uart: support async phys
2015-07-19 23:37:00 +02:00
a99aa9c7fd
uart: rename wishbone to bridge
2015-05-09 16:24:28 +02:00
fb5397aa82
uart: remove litescope dependency for UARTWishboneBridge and remove frontend
2015-05-09 16:08:20 +02:00
3ebe877fd2
use similar names for wishbone bridges and move wishbone drivers to [core]/software
2015-05-02 16:22:30 +02:00
8aa3fb3eb7
com/uart: add tx and rx fifos.
...
Since ressource usage is low with default depth of 16 (implemented in RAM LUTs) we don't keep old behaviour.
Tested successfully with BIOS and flterm.
2015-05-01 15:59:26 +02:00
7fc96da51c
misoclib/com/uart: remove liteeth dependency (copy/paste error)
2015-04-28 18:53:46 +02:00
2ccb5655c9
global: more pep8
...
we will have to continue the work... volunteers are welcome :)
2015-04-13 18:02:26 +02:00
fc68d915c1
global: pep8 (E261, E271)
2015-04-13 17:16:12 +02:00
01ba965d0c
global: pep8 (E401)
2015-04-13 16:56:25 +02:00
f68423f423
global: pep8 (E302)
2015-04-13 16:47:22 +02:00
d9e09707ae
global: pep8 (replace tabs with spaces)
2015-04-13 16:19:55 +02:00
767d45727a
uart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported on Windows since based on pty).
2015-03-12 16:57:38 +01:00
b157031e8a
uart/sim: add pty (optional, to use flterm)
2015-03-09 23:29:06 +01:00
d20b9c2221
uart: pass *args, **kwargs to sim phy
2015-03-06 12:08:10 +01:00
af66ca7bad
uart: add phy autodetect function
2015-03-06 10:19:29 +01:00
200791c81d
uart: generate ack for rx (serialboot OK with sim)
2015-03-04 00:57:37 +01:00
f58394f6af
soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
2015-03-01 18:25:47 +01:00
096e95cb59
uart: use data instead of d on endpoint's layouts (coherency with others cores)
2015-03-01 16:56:48 +01:00
1e6d1deae8
uart: add sim phy
2015-03-01 16:52:50 +01:00
bd4d3cd73b
uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
2015-03-01 12:14:34 +01:00
2c51adcd68
misoclib: better organization (create cores categories: cpu, mem, com, ...)
2015-02-28 09:40:44 +01:00
Florent Kermarrec
Robert Jordens